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ZPSD412A2V-25J

Description
Parallel I/O Port, 40 I/O, CMOS, PQCC68,
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size5MB,108 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Download Datasheet Parametric View All

ZPSD412A2V-25J Overview

Parallel I/O Port, 40 I/O, CMOS, PQCC68,

ZPSD412A2V-25J Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Objectid1414853804
Reach Compliance Codeunknown
YTEOL0
Other featuresGENERAL PURPOSE ZPLD
maximum clock frequency33.33 MHz
External data bus width8
JESD-30 codeS-PQCC-J68
JESD-609 codee0
Number of I/O lines40
Number of ports5
Number of terminals68
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC68,1.0SQ
Package shapeSQUARE
Package formCHIP CARRIER
Certification statusNot Qualified
Maximum supply voltage5.5 V
Minimum supply voltage2.7 V
Nominal supply voltage3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
uPs/uCs/peripheral integrated circuit typePARALLEL IO PORT, GENERAL PURPOSE
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