CS5151
CS5151
CPU 4-Bit Nonsynchronous Buck Controller
Description
The CS5151 is a 4-bit nonsyn-
chronous N-Channel buck con-
troller. It is designed to provide
unprecedented transient response
for today’s demanding high-densi-
ty, high-speed logic. The regulator
operates using a proprietary control
method, which allows a 100ns
response time to load transients.
The CS5151 is designed to operate
over a 4.25-16V range (V
CC
) using
12V to power the IC and 5V as the
main supply for conversion.
The CS5151 is specifically designed
to power Pentium
®
processors with
MMX™ Technology and other high
performance core logic. It includes
the following features: on board,
4-bit DAC, short circuit protection,
1.0% output tolerance, V
CC
monitor,
and programmable soft start capa-
bility. The CS5151 is upwards com-
patible with the 5-bit CS5156, allow-
ing the mother board designer the
capability of using either the
CS5151 or the CS5156 with no
change in layout. The CS5151 is
available in 16 pin surface mount
and DIP packages.
Features
s
N-Channel Design
s
Excess of 1MHz Operation
s
100ns Transient Response
s
4-Bit DAC
s
Upward Compatible with
5-Bit CS5155/5156 and
Adjustable CS5120/5121
s
30ns Gate Rise/Fall Times
s
1% DAC Accuracy
s
5V & 12V Operation
s
Remote Sense
s
Programmable Soft Start
s
Lossless Short Circuit
Protection
Application Diagram
Switching Power Supply for core logic - Pentium
®
processor with MMX™ Technology
12V
5V
s
V
CC
Monitor
s
Adaptive Voltage
Positioning
s
V
2
™ Control Topology
s
Current Sharing
s
Overvoltage Protection
0.1µF
1200µF/16V x 3
AlEl
IRL3103
2µH
2.1V to 3.5V @ 13A
V
CC1
V
CC2
V
ID0
V
ID1
V
ID2
V
ID3
V
ID0
V
ID1
V
ID2
V
ID3
C
OFF
330pF
SS
0.1µF
0.33µF
COMP
LGnd
V
GATE
CS5151
MBR735
Package Options
3
1,2
16 Lead SO Narrow & PDIP
1200µF/16V x 5
AlEl
PGnd
V
FB
V
FFB
3.3k
V
ID0
V
ID1
V
ID2
V
ID3
SS
NC
C
OFF
V
FFB
1
V
FB
COMP
LGnd
V
CC1
NC
PGnd
V
GATE
V
CC2
100pF
V
2
is a trademark of Switch Power, Inc.
Pentium is a registered trademark and MMX is a trademark of Intel Corporation.
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
Rev. 1/5/99
1
A
®
Company
CS5151
Absolute Maximum Ratings
Pin Name
Max Operating Voltage
Max Current
V
CC1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25mA DC/1.5A peak
V
CC2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA DC/1.5A peak
SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-100µA
COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200µA
V
FB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2µA
C
OFF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2µA
V
FFB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2µA
V
ID0
- V
ID3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-50µA
V
GATE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mA DC/1.5A peak
LGnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25mA
PGnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mA DC/1.5A peak
Operating Junction Temperature, T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .°0 to 150°C
Lead Temperature Soldering
Wave Solder (through hole styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 sec. max, 260°C peak
Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 sec. max above 183°C, 230°C peak
Storage Temperature Range, T
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65° to 150°C
ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Electrical Characteristics:
0°C < T
A
< +70°C; 0°C < T
J
< +85°C; 8V < V
CC1
< 14V; 5V < V
CC2
< 14V; DAC Code: V
ID2
= V
ID1
=
V
ID0
= 1; V
ID3
= 0; CV
GATE
= 1nF; C
OFF
= 330pF; C
SS
= 0.1µF, unless otherwise specified.
TEST CONDITIONS
MIN
TYP
PARAMETER
MAX
UNIT
s
Error Amplifier
V
FB
Bias Current
Open Loop Gain
Unity Gain Bandwidth
COMP SINK Current
COMP SOURCE Current
COMP CLAMP Current
COMP High Voltage
COMP Low Voltage
PSRR
s
V
CC1
Monitor
Start Threshold
Stop Threshold
Hysteresis
s
DAC
Input Threshold
Input Pull Up Resistance
Pull Up Voltage
Accuracy
V
ID3
V
ID2
V
ID1
V
ID0
1
1
1
1
1
1
1
0
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
V
FB
= 0V
1.25V < V
COMP
< 4V; Note 1
Note 1
V
COMP
= 1.5V; V
FB
= 3V; V
SS
> 2V
V
COMP
= 1.2V; V
FB
= 2.7V; V
SS
= 5V
V
COMP
= 0V; V
FB
= 2.7V
V
FB
= 2.7V; V
SS
= 5V
V
FB
=3V
8V < V
CC1
< 14V @ 1kHz; Note 1
50
500
0.4
30
0.4
4.0
60
0.3
60
3000
2.5
50
1.0
4.3
160
85
1.0
8.0
70
1.6
5.0
600
µA
dB
kH
mA
µA
mA
V
mV
dB
Output switching
Output not switching
Start-Stop
3.75
3.70
3.90
3.85
50
4.05
4.00
V
V
mV
V
ID0
, V
ID1
, V
ID2
, V
ID3
V
ID0
, V
ID1
, V
ID2
, V
ID3
Measure V
FB
= V
COMP
, 25°C
≤
T
J
≤
85°C
1.00
25
4.85
1.25
50
5.00
2.40
100
5.15
1.0
1.2564
2.1614
2.2624
2.3634
2.4644
2.5654
2.6664
2.7674
2.8684
2.9694
3.0704
V
kΩ
V
%
V
V
V
V
V
V
V
V
V
V
V
1.2315
2.1186
2.2176
2.3166
2.4156
2.5146
2.6136
2.7126
2.8116
2.9106
3.0096
2
1.2440
2.1400
2.2400
2.3400
2.4400
2.5400
2.6400
2.7400
2.8400
2.9400
3.0400
CS5151
Electrical Characteristics:
0°C < T
A
< +70°C; 0°C < T
J
< +85°C; 8V < V
CC1
< 14V; 5V < V
CC2
< 14V; DAC Code: V
ID2
= V
ID1
=
V
ID0
= 1; V
ID3
= 0; CV
GATE
= 1nF; C
OFF
= 330pF; C
SS
= 0.1µF, unless otherwise specified.
TEST CONDITIONS
MIN
TYP
PARAMETER
MAX
UNIT
s
DAC: continued
V
ID3
V
ID2
V
ID1
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
V
ID0
0
1
0
1
0
3.1086
3.2076
3.3066
3.4056
3.5046
3.1400
3.2400
3.3400
3.4400
3.5400
3.1714
3.2724
3.3734
3.4744
3.5754
V
V
V
V
V
s
V
GATE
Out SOURCE Sat at 100mA
Out SINK Sat at 100mA
Out Rise Time
Out Fall Time
Shoot-Through Current
V
GATE
Resistance
V
GATE
Schottky
s
Soft Start (SS)
Charge Time
Pulse Period
Duty Cycle
COMP Clamp Voltage
V
FFB
SS Fault Disable
High Threshold
s
PWM Comparator
Transient Response
V
FFB
Bias Current
s
Supply Current
I
CC1
I
CC2
Operating I
CC1
Operating I
CC2
s
C
OFF
Normal Charge Time
Extension Charge Time
Discharge Current
s
Time Out Timer
Time Out Time
Fault Mode Duty Cycle
Measure V
CC2
– V
GATE
Measure V
GATE
– VPGnd;
1V < V
GATE
< 9V; V
CC1
= V
CC2
= 12V
9V > V
GATE
> 1V; V
CC1
= V
CC2
= 12V
Note 1
Resistor to LGnd
LGnd to V
GATE
@ 10mA
1.2
1.0
30
30
20
50
600
2.0
1.5
50
50
50
100
800
V
V
ns
ns
mA
kΩ
mV
(Charge Time/Pulse Period)
×
100
V
FB
= 0V; V
SS
= 0
V
GATE
= Low
1.6
25
1.0
0.50
0.9
3.3
100
3.3
0.95
1.0
2.5
5.0
200
6.0
1.10
1.1
3.0
ms
ms
%
V
V
V
V
FFB
= 0 to 5V to V
GATE
= 9V to 1V;
V
CC1
= V
CC2
= 12V
V
FFB
= 0V
100
0.3
125
ns
µA
No Switching
No Switching
V
FB
= COMP = V
FFB
V
FB
= COMP = V
FFB
8.5
1.6
8
2
13.5
3.0
13
5
mA
mA
mA
mA
V
FFB
= 1.5V; V
SS
= 5V
V
SS
= V
FFB
= 0
C
OFF
to 5V; V
FB
>1V
1.0
5.0
5.0
1.6
8.0
2.2
11.0
µs
µs
mA
V
FB
= V
COMP
; V
FFB
= 2V;
Record V
GATE
Pulse High Duration
V
FFB
= 0V
10
35
30
50
50
65
µs
%
Note 1: Guaranteed by design, not 100% tested in production.
3
CS5151
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
16L SO Narrow & PDIP
1,2,3,4
V
ID0
– V
ID3
Voltage ID DAC input pins. These pins are internally pulled up to 5V
providing logic ones if left open. The DAC range is 2.14V to 3.54V with
100mV increments. V
ID0
- V
ID3
select the desired DAC output voltage.
Leaving all 4 DAC input pins open results in a DAC output voltage of
1.244V, allowing for adjustable output voltage, using a traditional resis-
tor divider.
Soft Start Pin. A capacitor from this pin to LGnd in conjunction with
internal 60µA current source provides soft start function for the con-
troller. This pin disables fault detect function during Soft Start. When a
fault is detected, the soft start capacitor is slowly discharged by internal
2µA current source setting the time out before trying to restart the IC.
Charge/discharge current ratio of 30 sets the duty cycle for the IC when
the regulator output is shorted.
No connection.
A capacitor from this pin to ground sets the time duration for the on
board one shot, which is used for the constant off time architecture.
Fast feedback connection to the PWM comparator. This pin is connected
to the regulator output. The inner feedback loop terminates on time.
Boosted power for the gate driver.
MOSFET driver pin capable of 1.5A peak switching current.
High current ground for the IC. The MOSFET driver is referenced to this
pin. Input capacitor ground and the anode of the Schottky diode should
be tied to this pin.
Input power for the IC.
Signal ground for the IC. All control circuits are referenced to this pin.
Error amplifier compensation pin. A capacitor to ground should be pro-
vided externally to compensate the amplifier.
Error amplifier DC feedback input. This is the master voltage feedback
which sets the output voltage. This pin can be connected directly to the
output or a remote sense trace.
5
SS
6, 12
7
8
9
10
11
NC
C
OFF
V
FFB
V
CC2
V
GATE
PGnd
13
14
15
16
V
CC1
LGnd
COMP
V
FB
4
CS5151
Block Diagram
V
CC2
V
CC1
-
+
3.90V
3.85V
V
CC1
Monitor
Comparator
5V
-
60µA
0.7V
+
SS Low
Comparator
R
S
Q
Q
V
GATE
FAULT
FAULT
PGnd
SS
2µA
+
-
SS High
Comparator
FAULT
Latch
V
ID0
V
ID1
V
ID2
V
ID3
4 BIT
DAC
+
-
Error
Amplifier
2.5V
PWM
Comparator
-
GATE = ON
GATE = OFF
C
OFF
One Shot
R
S
Q
V
FB
COMP
V
FFB
Slow Feedback
+
Maximum
On-Time
Timeout
Normal
Off-Time
Timeout
R
S
Q
Q
PWM
Latch
Fast Feedback
-
+
Extended
Off-Time
Timeout
V
FFB
Low
Comparator
Off-Time
Timeout
C
OFF
LGnd
1V
PWM
COMP
Time Out
Timer
(30µs)
Edge Triggered
Applications Information
Theory of Operation
V
2
™ Control Method
The V
2
™ method of control uses a ramp signal that is gen-
erated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is gen-
erated from the output voltage itself. This control scheme
differs from traditional techniques such as voltage mode,
which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.
PWM
Comparator
+
C
–
Ramp
Signal
COMP
Error
Signal
V
GATE
V
FFB
Output
Voltage
Feedback
V
FB
–
Error
Amplifier
E
+
Reference
Voltage
Figure 1: V
2
™ Control Diagram
The V
2
™ control method is illustrated in Figure 1. The out-
put voltage is used to generate both the error signal and the
ramp signal. Since the ramp signal is simply the output
voltage, it is affected by any change in the output regard-
less of the origin of that change. The ramp signal also con-
tains the DC portion of the output voltage, which allows
the control circuit to drive the main switch to 0% or 100%
duty cycle as required.
A change in line voltage changes the current ramp in the
inductor, affecting the ramp signal, which causes the V
2
™
control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V
2
™ control scheme has the
same advantages in line transient response.
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined
only by the comparator response time and the transition
speed of the main switch. The reaction time to an output
load step has no relation to the crossover frequency of the
error signal loop, as in traditional control methods.
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal loop.
The main purpose of this ‘slow’ feedback loop is to provide
DC accuracy. Noise immunity is significantly improved,
since the error amplifier bandwidth can be rolled off at a low
frequency. Enhanced noise immunity improves remote sens-
5
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