Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDIP14, 0.300 INCH, DIP-14
| Parameter Name | Attribute value |
| Is it lead-free? | Lead free |
| Is it Rohs certified? | conform to |
| Parts packaging code | DIP |
| package instruction | DIP, |
| Contacts | 14 |
| Reach Compliance Code | compliant |
| Other features | MAX FAN OUT OF 10 74LS LOAD PER OUTPUT; MAX RISE TIME CAPTURED |
| series | CMOS/TTL |
| Input frequency maximum value (fmax) | 8 MHz |
| JESD-30 code | R-PDIP-T14 |
| length | 19.4 mm |
| Load capacitance (CL) | 25 pF |
| Logic integrated circuit type | SILICON DELAY LINE |
| Number of functions | 1 |
| Number of taps/steps | 5 |
| Number of terminals | 14 |
| Maximum operating temperature | 70 °C |
| Minimum operating temperature | |
| Output polarity | TRUE |
| Package body material | PLASTIC/EPOXY |
| encapsulated code | DIP |
| Package shape | RECTANGULAR |
| Package form | IN-LINE |
| Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
| programmable delay line | NO |
| Certification status | Not Qualified |
| Maximum seat height | 4.31 mm |
| Maximum supply voltage (Vsup) | 5.25 V |
| Minimum supply voltage (Vsup) | 4.75 V |
| Nominal supply voltage (Vsup) | 5 V |
| surface mount | NO |
| technology | CMOS |
| Temperature level | COMMERCIAL |
| Terminal form | THROUGH-HOLE |
| Terminal pitch | 2.54 mm |
| Terminal location | DUAL |
| Maximum time at peak reflow temperature | NOT SPECIFIED |
| Total delay nominal (td) | 300 ns |
| width | 7.62 mm |
| Base Number Matches | 1 |
京公网安备 11010802033920号
EEWORLD
