Preliminary
GS880Z18/36T-11/100/80/66
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• 512K x 18 and 256K x 36 configurations
• User configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• Pin compatible with 2M, 4M and 16M (future) devices
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• Clock Control, registered address, data, and control
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
8Mb Pipelined and Flow Through
100 MHz–66 MHz
3.3 V V
DD
Synchronous NBT SRAMs
2.5 V and 3.3 V V
DDQ
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS880Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, in addition to the rising-edge-triggered
registers that capture input signals, the device incorporates a
rising-edge-triggered output register. For read cycles, pipelined
SRAM output data is temporarily stored by the edge triggered
output register during the access cycle and then released to the
output drivers at the next rising edge of clock.
The GS880Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
-11
Pipeline
3-1-1-1
Flow Through
2-1-1-1
t
Cycle
t
KQ
I
DD
t
KQ
t
Cycle
I
DD
10 ns
4.5 ns
210 mA
11 ns
15 ns
150 mA
-100
10 ns
4.5 ns
210 mA
12 ns
15 ns
150 mA
-80
12.5 ns
4.8 ns
190 mA
14 ns
15 ns
130 mA
-66
15 ns
5 ns
170 mA
18 ns
20 ns
130 mA
Functional Description
The GS880Z18/36T is an 8Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock
Address
Read/Write
A
R
B
W
Q
A
C
R
D
B
Q
A
1/25
D
W
Q
C
D
B
E
R
D
D
Q
C
F
W
Q
E
D
D
Q
E
Flow Through
Data I/O
Pipelined
Data I/O
Rev: 1.10 8/2000
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
.
GS880Z18/36T-11/100/80/66
100 Pin TQFP Pin Descriptions
Pin Location
37, 36
35, 34, 33, 32, 100, 99, 83, 82,
81, 50, 49, 48, 47, 46, 45, 44
80
89
93
94
95
96
88
98
97
92
86
85
87
58, 59, 62,63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
51, 52, 53, 56, 57, 75, 78, 79,
1, 2, 3, 6, 7, 25, 28, 29, 30, 95,
96
51, 52, 53, 56, 57, 58, 59, 62,63
68, 69, 72, 73, 74, 75, 78, 79, 80
1, 2, 3, 6, 7, 8, 9, 12, 13
64
14
31
15, 16, 41, 65, 91
5,10, 17, 21, 26, 40, 55, 60, 67,
71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
38, 39, 42, 43, 66, 84
Symbol
A
0
, A
1
A
2
–A
17
A
18
CK
B
A
B
B
B
C
B
D
W
E
1
E
2
E
3
G
ADV
CKE
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
NC
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
DQ
C1
–DQ
C9
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
NC
Type
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
I/O
I/O
-
I/O
I/O
I/O
I/O
In
In
In
In
In
In
-
Description
Burst Address Inputs; preload the burst counter
Address Inputs
Address Input (x18 Version Only)
Clock Input Signal
Byte Write signal for data inputs DQ
A1
-DQ
A9
; active low
Byte Write signal for data inputs DQ
B1
-DQ
B9
; active low
Byte Write signal for data inputs DQ
C1
-DQ
C9
; active low (x32/x36 Versions Only)
Byte Write signal for data inputs DQ
D1
-DQ
D9
; active low (x32/x36 Versions Only)
Write Enable; active low
Chip Enable; active low
Chip Enable; active high; for self decoded depth expansion
Chip Enable; active low, for self decoded depth expansion
Output Enable; active low
Advance / Load—Burst address counter control pin
Clock Input Buffer Enable; active low
Byte A Data Input and Output pins (x18 Version Only)
Byte B Data Input and Output pins (x18 Version Only)
No Connect (x18 Version Only)
Byte A Data Input and Output pins (x36 Versions Only)
Byte B Data Input and Output pins (x36 Versions Only)
Byte C Data Input and Output pins (x36 Versions Only)
Byte D Data Input and Output pins (x36 Versions Only)
Power down control; active high
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low
3.3 V power supply
Ground
3.3 V output power supply for noise reduction
No Connect
18, 19, 22, 23, 24, 25, 28, 29, 30 DQ
D1
–DQ
D9
Rev: 1.10 8/2000
4/25
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
京公网安备 11010802033920号
EEWORLD
