TC55VBM416AFTN55
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
1,048,576-WORD BY 16-BIT/2,097,152-WORD BY 8-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55VBM416AFTN is a 16,777,216-bit static random access memory (SRAM) organized as 1,048,576 words
by 16 bits/2,097,152 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device
operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and low
power at an operating current of 3 mA/MHz and a minimum cycle time of 55 ns. It is automatically placed in
low-power mode at 0.9
µA
standby current (at V
DD
=
3 V, Ta
=
25°C, typical) when chip enable ( CE1 ) is asserted
high or (CE2) is asserted low. There are three control inputs. CE1 and CE2 are used to select the device and for
data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB )
provides lower and upper byte access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating extreme
temperature range of
−40°
to 85°C, the TC55VBM416AFTN can be used in environments exhibiting extreme
temperature conditions. The TC55VBM416AFTN is available in a plastic 48-pin thin-small-outline package
(TSOP).
FEATURES
•
•
•
•
•
•
•
Low-power dissipation
Operating: 9 mW/MHz (typical)
Single power supply voltage of 2.3 to 3.6 V
Power down features using CE1 and CE2
Data retention supply voltage of 1.5 to 3.6 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
−40°
to 85°C
Standby Current (maximum):
3.6 V
3.0 V
15
µA
8
µA
•
Access Times (maximum):
Access Time
CE1
Access Time
55 ns
55 ns
55 ns
30 ns
CE2
OE
Access Time
Access Time
•
Package:
TSOPⅠ48-P-1220-0.50
(Weight:0.51 g typ)
PIN ASSIGNMENT
(TOP VIEW)
48 PIN TSOP
PIN NAMES
A0~A19
1
48
A-1~A19
CE1
, CE2
Address Inputs (Word Mode)
Address Inputs (Byte Mode)
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Data Inputs/Outputs
Byte (×8 mode) Enable
Power
Ground
No Connection
Option
R/W
OE
LB ,
UB
24
(Normal)
25
I/O1~I/O16
BYTE
V
DD
GND
NC
OP*
*: OP pin must be open or connected to GND.
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
A15
17
A17
33
I/O3
2
A14
18
A7
34
I/O11
3
A13
19
A6
35
I/O4
4
A12
20
A5
36
I/O12
5
A11
21
A4
37
V
DD
6
A10
22
A3
38
I/O5
7
A9
23
A2
39
8
A8
24
A1
40
9
A19
25
A0
41
10
NC
26
CE1
11
R/W
27
GND
43
12
CE2
28
OE
13
OP
29
I/O1
14
UB
15
LB
31
I/O2
16
A18
32
I/O10
48
A16
30
I/O9
42
44
I/O13 I/O6
I/O14 I/O7
I/O15 I/O8
45
46
47
I/O16 GND
BYTE
/A-1
2002-08-29
1/14
TC55VBM416AFTN55
(Ta
= −
40° to 85°C, V
DD
=
2.7 to 3.6 V)
READ CYCLE
SYMBOL
t
RC
t
ACC
t
CO1
t
CO2
t
OE
t
BA
t
COE
t
OEE
t
BE
t
OD
t
ODO
t
BD
t
OH
Read Cycle Time
Address Access Time
Chip Enable(
CE1
) Access Time
Chip Enable(CE2) Access Time
Output Enable Access Time
Data Byte Control Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Data Byte Control High to Output High-Z
Output Data Hold Time
PARAMETER
MIN
55
5
0
5
10
MAX
55
55
55
30
55
25
25
25
ns
UNIT
AC CHARACTERISTICS AND OPERATING CONDITIONS
WRITE CYCLE
SYMBOL
t
WC
t
WP
t
CW
t
BW
t
AS
t
WR
t
ODW
t
OEW
t
DS
t
DH
Note:
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Byte Control to End of Write
Address Setup Time
Write Recovery Time
R/W Low to Output High-Z
R/W High to Output Active
Data Setup Time
Data Hold Time
PARAMETER
MIN
55
40
45
45
0
0
0
25
0
MAX
25
ns
UNIT
t
OD
, t
ODO
, t
BD
and t
ODW
are specified in time when an output becomes high impedance, and are not judged depending on
an output voltage level.
2002-08-29
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Embedded System
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