ATA8201/ATA8202
UHF ASK/FSK Receiver
DATASHEET
Features
●
Transparent RF receiver ICs for 315MHz (Atmel
®
ATA8201) and 433.92MHz
(Atmel ATA8202) with high receiving sensitivity
●
Fully integrated PLL with low phase noise VCO, PLL, and loop filter
●
High FSK/ASK sensitivity:
●
●
●
●
–105dBm (Atmel ATA8201, FSK, 9.6Kbits/s, Manchester, BER 10
-3
–114dBm (Atmel ATA8201, ASK, 2.4Kbits/s, Manchester, BER 10
-3
)
–104dBm (Atmel ATA8202, FSK, 9.6Kbits/s, Manchester, BER 10
-3
)
–113dBm (Atmel ATA8202, ASK, 2.4Kbits/s, Manchester, BER 10
-3
)
●
Supply current: 6.5mA in Active Mode (3V, 25°C, ASK Mode)
●
Data rate: 1Kbit/s to 10Kbits/s Manchester ASK, 1Kbit/s to 20Kbits/s Manchester
FSK with four programmable bit rate ranges
●
Switching between modulation types ASK/FSK and different data rates possible in
≤
1ms typically, without hardware modification on board to allow different
modulation schemes
●
Low standby current: 50µA at 3V, 25°C
●
ASK/FSK receiver uses a low-IF architecture with high selectivity, blocking, and low
intermodulation (typical 3-dB blocking 68.0dBC at ±3MHz/74.0dBC at ±20.0MHz,
system I1dBCP = –31dBm/system IIP3 = –24dBm)
●
Telegram pause up to 52ms supported in ASK Mode
●
Wide bandwidth AGC to handle large out-of-band blockers above the system
I1dBCP
●
440-kHz IF frequency with 30-dB image rejection and 420-kHz IF bandwidth to
support PLL transmitters with standard crystals or SAW-based transmitters
●
RSSI (received signal strength indicator) with output signal dynamic range of 65dB
●
Low in-band sensitivity change of typically ±2.0dB within ±160-kHz center
frequency change in the complete temperature and supply voltage range
●
Sophisticated threshold control and quasi-peak detector circuit in the data slicer
●
Fast and stable XTO start-up circuit (> –1.4 kΩ worst-case start impedance)
●
Clock generation for microcontroller
●
ESD protection at all pins (±4kV HBM, ±200V MM, ±500V FCDM)
4971G-INDCO-09/14
●
Dual supply voltage range: 2.7V to 3.3V or 4.5V to 5.5V
●
Temperature range: –40°C to +85°C
●
Small 5mm
×
5mm QFN24 package
Applications
●
Industrial/aftermarket keyless entry and tire pressure monitoring systems
●
Alarm, telemetering and energy metering systems
●
Remote control systems for consumer and industrial markets
●
Access control systems
●
Home automation
●
Home entertainment
●
Toys
Benefits
●
Supports header and blanking periods of protocols common in RKE and TPM systems (up to 52ms in ASK Mode)
●
All RF relevant functions are integrated. The single-ended RF input is suited for easy adaptation to
λ
/ 4 or printed-loop
antennas
●
Allows a low-cost application with only 8 passive components
●
Optimal bandwidth maximizes sensitivity while maintaining SAW transmitter compatibility
●
Clock output provides an external microcontroller crystal-precision time reference
●
Well suited for use with Atmel
®
PLL transmitter ATA8401/ATA8402/ATA8403/ATA8404/ATA8405
2
ATA8201/ATA8202 [DATASHEET]
4971G–INDCO–09/14
1.
General Description
The Atmel
®
ATA8201/ATA8202 is a UHF ASK/FSK transparent receiver IC with low power consumption supplied in a small
QFN24 package (body 5mm
×
5mm, pitch 0.65mm). Atmel ATA8202 is used in the 433MHz to 435MHz band of operation,
and Atmel ATA8201 in 313MHz to 317MHz.
For improved image rejection and selectivity, the IF frequency is fixed to 440kHz. The IF block uses an 8th-order band pass
yielding a receive bandwidth of 420kHz. This enables the use of the receiver in both SAW- and PLL-based transmitter
systems utilizing various types of data-bit encoding such as pulse width modulation, Manchester modulation, variable pulse
modulation, pulse position modulation, and NRZ. Prevailing encryption protocols such as Keeloq
®
are easily supported due
to the receiver’s ability to hold the current data slicer threshold for up to 52ms when incoming RF telegrams contain a
blanking interval. This feature eliminates erroneous noise from appearing on the demodulated data output pin, and simplifies
software decoding algorithms. The decoding of the data stream must be carried out by a connected microcontroller device.
Because of the highly integrated design, the only required RF components are for the purpose of receiver antenna matching.
Atmel ATA8201 and Atmel ATA8202 support Manchester bit rates of 1Kbit/s to 10Kbits/s in ASK and 1Kbit/s to 20Kbits/s in
FSK mode. The four discrete bit rate passbands are selectable and cover 1.0Kbit/s to 2.5Kbits/s, 2.0Kbits/s to 5.0Kbits/s,
4.0Kbits/s to 10.0Kbits/s, and 8.0Kbits/s to 10.0Kbits/s or 20.0Kbits/s (for ASK or FSK, respectively). The receiver contains
an RSSI output to provide an indication of received signal strength and a SENSE input to allow the customer to select a
threshold below which the DATA signal is gated off. ASK/FSK and bit rate ranges are selected by the connected
microcontroller device via pins ASK_NFSK, BR0, and BR1.
Figure 1-1. System Block Diagram
ATA8201/ATA8202
Digital Control
Logic
Power
Supply
Antenna
RF Receiver
(LNA, Mixer,
VCO, PLL,
IF Filter,
RSSI Amp.,
Demodulator)
Microcontroller
4 ... 8
Microcontroller
Interface
XTO
ATA8201/ATA8202 [DATASHEET]
4971G–INDCO–09/14
3
Figure 1-2. Pinning QFN24
ASK_NFSK
DATA_OUT
CDEM
BR1
BR0
TEST2
TEST1
CLK_OUT
CLK_OUT_CTRL1
CLK_OUT_CTRL0
ENABLE
1
2
3
4
5
6
24 23 22 21 20 19
18
17
16
15
14
7
8
13
9 10 11 12
RX
TEST3
RSSI
SENSE_CTRL
SENSE
LNA_IN
LNA_GND
GND
DVCC
XTAL2
VS5V
Table 1-1.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin Description
Symbol
TEST2
TEST1
CLK_OUT
CLK_OUT_CTRL1
CLK_OUT_CTRL0
ENABLE
XTAL2
XTAL1
DVCC
VS5V
VS3V_AVCC
GND
LNA_GND
LNA_IN
SENSE
SENSE_CTRL
RSSI
TEST3
RX
BR0
BR1
ASK_NFSK
CDEM
DATA_OUT
GND
Function
Test pin, during operation at GND
Test pin, during operation at GND
Output to clock a connected microcontroller
Input to control CLK_OUT (MSB)
Input to control CLK_OUT (LSB)
Input to enable the XTO
Reference crystal
Reference crystal
Digital voltage supply blocking
Power supply input for voltage range 4.5V to 5.5V
Power supply input for voltage range 2.7V to 3.3V
Ground
RF ground
RF input
Sensitivity control resistor
Sensitivity selection
Low: Normal sensitivity, High: Reduced sensitivity
Output of the RSSI amplifier
Test pin, during operation at GND
Input to activate the receiver
Bit rate selection, LSB
Bit rate selection, MSB
FSK/ASK selection
Low: FSK, High: ASK
Capacitor to adjust the lower cut-off frequency data filter
Data output
Ground/backplane (exposed die pad)
4
ATA8201/ATA8202 [DATASHEET]
4971G–INDCO–09/14
VS3V_AVCC
XTAL1
Figure 1-3. Block Diagram
ASK
FSK
ASK/FSK
Control
IF Amp
SENSE
SENSE_CTRL
IF Filter
GND
LPF
Standby
Logic Control
RX
Data
Slicer
CDEM
ASK/FSK
Demo-
dulator
Power
Supply
VS3V_AVCC
VS5V
ASK_NFSK
DATA_OUT
BR0
BR1
DVCC
IF Amp
XTO
Div. by 3, 6, 12
CLK_OUT_CTRL1
CLK_OUT_CTRL0
CLK_OUT
RSSI
LPF
LNA_IN
LNA_GND
PLL
(/24, /32)
XTO
ENABLE
TEST1
LNA
VCO
TEST2
TEST3
XTAL2
XTAL1
ATA8201/ATA8202 [DATASHEET]
4971G–INDCO–09/14
5
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