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2
DS479DB2
CDB43L43
Figure 18.FFT of 1 kHz Sine Wave at 3.0 V ...................................................... 18
Figure 19.Silkscreen Top ................................................................................... 19
Figure 20.Bottom Side ....................................................................................... 20
Figure 21.Top Side ............................................................................................. 21
DS479DB2
3
CDB43L43
1. CDB43L43 SYSTEM OVERVIEW
The CDB43L43 evaluation board is an excellent
means of quickly evaluating the CS43L43. The
CS8415A digital audio interface receiver provides
an easy interface to digital audio signal sources in-
cluding the majority of digital audio test equip-
ment. The evaluation board also allows the user to
supply clocks and data through a 10-pin header for
system development.
The CDB43L43 schematic has been partitioned
into 10 schematics shown in Figures 2 through 11.
Each partitioned schematic is represented in the
system diagram shown in Figure 1. Notice that the
the system diagram also includes the interconnec-
tions between the partitioned schematics.
5. HEADPHONE OUTPUT
A 1/8 inch, stereo headphone jack is included on
the evaluation board for connecting 16 ohm or
greater headphones to the CS43L43. If no head-
phones are connected to the 1/8 inch jack, then a 16
ohm resistor is connected to each of the CS43L43
headphone outputs, HP_A and HP_B. This is use-
ful when evaluating the CS43L43 headphone am-
plifier with test equipment that has high-impedance
inputs. RCA jacks are also provided on the head-
phone outputs for easy connection to test equip-
ment.
6. INPUT/OUTPUT FOR CLOCKS AND
DATA
The evaluation board has been designed to allow
interfacing to external systems via the 10-pin head-
er, HDR1. This header allows the evaluation board
to accept externally generated clocks and data. The
schematic for the clock/data I/O is shown in
Figure 10.
2. CS43L43 DIGITAL TO ANALOG
CONVERTER
A description of the CS43L43 is included in the
CS43L43 datasheet.
3. CS8415A DIGITAL AUDIO
RECEIVER
The system receives and decodes the standard
S/PDIF data format using a CS8415A Digital Au-
dio Receiver, Figure 4. The outputs of the
CS8415A include a serial bit clock, serial data, left-
right clock (FSYNC), de-emphasis control and a
256 Fs master clock. The operation of the
CS8415A and a discussion of the digital audio in-
terface are included in the CS8415A datasheet.
The evaluation board has been designed such that
the input can be either optical or coax, see Figure 5.
However, both inputs cannot be driven simulta-
neously.
7. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by five
binding posts (GND, +5 V, VL, VA, VA_HP), see
Figure 12. The +5 V input supplies power to the
+5 Volt digital circuitry (VA_+5, VD_+5), while
the VL input supplies power to the Voltage Level
Converters and the CS43L43 VL pin. VA and
VA_HP supply power to the CS43L43. For ease of
use, it is possible to connect VA, VA_HP and VL
to the same supply.
WARNING:
VA and VL must be between +1.7 V
and +3.6 V. VA_HP must be between +0.9 V and
+3.6 V. Operation outside of this range can cause
permanent damage to the device. See the CS43L43
datasheet for more details.
4. CS8415A DATA FORMAT
The CS8415A data format is selected through the
DIP switch. See Table 2 for details.
4
DS479DB2
CDB43L43
8. GROUNDING AND POWER SUPPLY
DECOUPLING
The CS43L43 requires careful attention to power
supply and grounding arrangements to optimize
performance. Figure 9 details the power distribu-
tion used on this board. The decoupling capacitors
are located as close to the CS43L43 as possible.
Extensive use of ground plane fill on both the ana-
log and digital sections of the evaluation board
yields large reductions in radiated noise.
11. CDB43L43 PERFORMANCE PLOTS
The CDB43L43 Rev A performance plots shown in
Figures 13 through 18 were generated using an Au-
dio Precision System Two Cascade with the S2-
AES17LP 20 kHz brickwall filter applied. All tests
were performed at a sampling rate of 48 kHz and
with VL, VA, and VA_HP set to the indicated volt-
age supply.
12. CDB43L43 REV A ERRATA
1) R20 and R30 have been stuffed with 0 ohm re-
sistors and 47 kohm pull-downs have been add-
ed to pins 3 and 28 of U4.
2) The DIP switch has been turned such that the
“open” position is denoted by the “1” on the
board.
3) R31 has been changed from a pull-up to a pull-
down.
4) A 1 Mohm pull-down has been added to U10
pin 8, located near R24.
The CDB43L43 was also modified to reflect the
changes made to the CS43L43 in Revision G. The
second circuit in Figure 3, page 8 of this datasheet
was removed, and the CS43L43 Revision G is
mounted on the CDB43L43 for evaluation.
9. CONTROL PORT SOFTWARE
The CDB43L43 is shipped with Windows based
software for interfacing with the CS43L43 control
port via the serial connector, J1. The software can
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