Document Revision History
Version History
Rev 1.0
Rev 2.0
Rev 3.0
Description of Change
Pre-Release version, Alpha customers only
Initial Public Release
Corrected typo in
Table 10-4,
Flash Endurance is 10,000 cycles. Addressed additional grammar
issues.
Added Package Pins to GPIO Table in Section 8. Removed reference to pin group 9 in
Table 10-5.
Replacing TBD Typical Min with values in
Table 10-17.
Editing grammar, spelling, consistency of
language throughout family. Updated values in Regulator Parameters,
Table 10-9,
External Clock
Operation Timing Requirements
Table 10-13,
SPI Timing,
Table 10-18,
ADC Parameters,
Table 10-24,
and IO Loading Coefficients at 10MHz,
Table 10-25.
Updated values in Power-On Reset Low Voltage,
Table 10-6.
Correcting package pin numbers in
Table 2-2,
PhaseA0
changed from 38 to 52,
PhaseB0
changed
from 37 to 51,
Index0
changed from 36 to 50, and
Home0
changed from 35 to 49. All pin changes in
Table 2-2 were do to data entry errors - This package pin-out has not changed
Added
Part 4.8,
added addition text to
Part 6.9
on POR reset, added the word “access” to FM Error
Interrupt in
Table 4-3,
removed min and max numbers; only documenting Typ. numbers for LVI in
Table 10-6.
Updated numbers in
Table 10-7
and
Table 10-8
with more recent data. Corrected typo in
Table 10-3
in
Pd characteristics.
Replace any reference to Flash Interface Unit with Flash Memory Module; changed example in
Part
2.2;
added note on V
REFH
and V
REFLO
in
Table 2-2
and
Table 11-1;
added note to Vcap pin in
Table 2-2;
corrected typo FIVAL1 and FIVAH1 in
Table 4-12;
removed unneccessary notes in
Table 10-12;
corrected temperature range in
Table 10-14;
added ADC calibration information to
Table 10-24
and new graphs in
Figure 10-21.
Clarification to
Table 10-23,
corrected Digital Input Current Low (pull-up enabled) numbers in
Table 10-5.
Removed text and Table 10-2; replaced with note to
Table 10-1.
Added 56F8123 information; edited to indicate differences in 56F8323 and 56F8123.Reformatted for
Freescale look and feel. Updated Temperature Sensor and ADC tables, then updated balance of
electrical tables for consistency throughout the family. Clarified I/O power description in
Table 2-2,
added note to
Table 10-7
and clarified
Section 12.3
.
Added output voltage maximum value and note to clarify in
Table 10-1;
also removed overall life
expectancy note, since life expectancy is dependent on customer usage and must be determined by
reliability engineering. Clarified value and unit measure for Maximum allowed P
D
in
Table 10-3.
Corrected note about average value for Flash Data Retention in
Table 10-4.
Added new
RoHS-compliant orderable part numbers in
Table 13-1.
Deleted formula for Max Ambient Operating Temperature (Automotive) and Max Ambient Operating
Temperature (Industrial) in
Table 10-4.
Added RoHS-compliance and “pb-free” language to back
cover.
Rev 4.0
Rev 5.0
Rev 6.0
Rev 7.0
Rev 8.0
Rev 9.0
Rev 10.0
Rev. 11.0
Rev 12.0
Rev 13.0
56F8323 Technical Data, Rev. 17
2
Freescale Semiconductor
Preliminary
Document Revision History
Version History
Rev 14.0
Description of Change
Added information/corrected state during reset in
Table 2-2.
Clarified external reference crystal
frequency for PLL in
Table 10-14
by increasing maximum value to 8.4MHz.
Replaced “Tri-stated” with an explanation in State During Reset column in
Table 2-2.
• Added the following note to the description of the TMS signal in
Table 2-2:
Note:
Always tie the TMS pin to V
DD
through a 2.2K resistor.
• Added the following note to the description of the TRST signal in
Table 2-2:
Note:
For normal operation, connect TRST directly to V
SS
. If the design is to be used in a debugging
environment, TRST may be tied to V
SS
through a 1K resistor.
Rev. 17
Changed the “Frequency Accuracy” specification in
Table 10-16
(was ±2.0%, is +2 / -3%).
Rev 15.0
Rev. 16
Please see http://www.freescale.com for the most current data sheet revision.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
3
56F8323/56F8123 General Description
Note:
Features in italics are NOT available in the 56F8123 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 32KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• One 6-channel PWM module
• Two 4-channel 12-bit ADCs
• Temperature Sensor
• One Quadrature Decoder
• One FlexCAN module
• Up to two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Two general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 27 GPIO lines
• 64-pin LQFP Package
RESET
5
6
3
3
OCR_DIS
V
CAP
4
V
DD
4
4
V
SS
V
DDA
2
V
SSA
PWM Outputs
Current Sense Inputs
Fault Inputs
PWMA or
SPI1 or
GPIOA
Program Controller
and Hardware
Looping Unit
JTAG/
EOnCE
Port
Digital Reg
Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Bit
Manipulation
Unit
Address
Generation Unit
Data ALU
16 x 16 + 36
−>
36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
4
4
5
AD0
AD1
VREF
TEMP_SENSE
PAB
PDB
CDBR
CDBW
Memory
Program Memory
16K x 16 Flash
2K x 16 RAM
4K x 16 Boot
Flash
Data Memory
4K x 16 Flash
4K x 16 RAM
R/W Control
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
4
Quadrature
Decoder 0 or
Quad
Timer A or
GPIO B
System Bus
Control
IPBus Bridge (IPBB)
3
Quad
Timer C or
SCI0 or
GPIOC
FlexCAN or
GPIOC
Peripheral
Device Selects
RW
Control
IPAB
IPWDB
IPRDB
2
Decoding
Peripherals
Clock
resets
PLL
SPI0 or
SCI1 or
GPIOB
4
COP/
Watchdog
Interrupt
Controller
System
O
Integration
R
Module
P
O
Clock
S
Generator*
C
XTAL or GPIOC
EXTAL or GPIOC
IRQA
*Includes On-Chip
Relaxation Oscillator
56F8323/56F8123 Block Diagram
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
5
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