LatticeECP2™ Standard Evaluation Board
User’s Guide
May 2007
Revision: ebdug18_01.3
Lattice Semiconductor
LatticeECP2 Standard Evaluation Board
User’s Guide
Introduction
The LatticeECP2 Standard Evaluation Board is a complete, integrated design, featuring a LatticeECP2 FPGA and
a variety of both application-specific and general-purpose peripheral interfaces. This board provides a convenient
platform to evaluate, test, and debug user designs, including designs requiring PCI/PCI-X. This board includes the
following features:
• LatticeECP2 FPGA device in 484 fpBGA package
• SPI Serial Flash device included for low-cost, non-volatile configuration storage
• PCI/PCI-X edge connector (188-pin) supporting Master or Target
– PCI 2.2 - 32/64 bit, 33/66 MHz, 3.3V
– PCI-X - 32/64 bit, 66/133 MHz, parity or ECC, 3.3V (Mode 1)
• RS-232 connector
• 33.33 MHz oscillator
• RJ-45 connector
• LCD connector
• Compact Flash connector
• Prototyping area with access to over 210 I/O pins
• Optional SMA/SMB connectors (up to eight) for high-speed clock and data interfacing
• 7-segment display, eight general purpose switches, two momentary switches, eight user LEDs, and various sta-
tus LEDs
• Required voltages supplied by PCI/PCI-X or one external 5V DC supply
• ispVM
®
System programming support
Figure 1. Lattice ECP2 Standard Evaluation Board
Electrical, Mechanical, and Environmental Specifications
The nominal board dimensions are 9.75 inches by 4.2 inches. The environmental specifications are as follows:
• Operating temperature: 0ºC to 55ºC
• Storage temperature: -40ºC to 75ºC
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Lattice Semiconductor
• Humidity: < 95% without condensation
LatticeECP2 Standard Evaluation Board
User’s Guide
• 5VDC input (+/- 10%) up to 4A, or 3.3V input from PCI/PCI-X backplane
Additional Resources
Additional resources relating to the LatticeECP2 Standard Evaluation Board (including updated documentation,
and sample programs) can be found at the following URL:
www.latticesemi.com/products/developmenthardware/fpgafspcboards/ecp2stardevaluationboard.cfm
Features
LatticeECP2 Device
This board features a LatticeECP2 FPGA with a 1.2V DC core in a 484-ball fpBGA package. A complete descrip-
tion of this device can be found in the LatticeECP2 Family Data Sheet available on the Lattice web site at www.lat-
ticesemi.com/ecp2.
On-Board Oscillator
The 3.3V oscillator socket at Y1 accepts both full-size (14-pin) and half-size (8-pin) oscillators, and will route the
oscillator output to a LatticeECP2 primary clock input or a PLL input, depending on the oscillator’s position in the
socket (see Figure 2).
When a full size oscillator is installed such that pin 1 of the oscillator aligns with pin 1 of the socket, the output of
the oscillator drives the primary clock at LatticeECP2 pin J21 (this is the default position). When pin 1 of the oscilla-
tor is aligned to pin 2 of the socket, the clock is routed to LatticeECP2 pin J21. When using a half size oscillator,
align pin 1 of the oscillator to pin 1 of the socket to drive the primary clock, or align pin 1 of the oscillator to pin 5 of
the socket to drive the PLL. Note that pin 1 of the oscillator is expected to be a no-connect pin.
Figure 2. Oscillator Options
Pin-1
Default
Position
Pin-16
3.3V
Pin-1
Half-Size
33.33 MHz
Pin-16
3.3V
Full-Size
33.33 MHz
Primary Clock
(J21)
Primary Clock
(J21)
GND
PLL Clock
(N21)
GND
PLL Clock
(N21)
Pin-1
Pin-16
3.3V
Pin-1
Pin-16
3.3V
Full-Size
33.33 MHz
Primary Clock
(J21)
Half-Size
33.33 MHz
Primary Clock
(J21)
GND
PLL Clock
(N21)
GND
PLL Clock
(N21)
SPI Serial Flash
SPI Serial Flash are available in three package styles, two of those packages, 8-pin SO and 16-pin SO, are sup-
ported by this board. In general, the 8-pin devices support densities up to 16Mb, while the 16-pin devices support
larger densities. The device chosen for inclusion on this board depends on the density of the installed LatticeECP2,
but the SPI Serial Flash will be large enough to allow two bitstreams to be stored simultaneously in order to support
SPIm mode.
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Lattice Semiconductor
LatticeECP2 Standard Evaluation Board
User’s Guide
The 8-pin device footprint is at U4; the 16-pin device footprint is at U5. Only one location can be populated at a
time.
Configuration/Programming Headers
Two programming headers are provided on the evaluation board, providing access to the LatticeECP2 JTAG port
and sysCONFIG™ port. The JTAG connector is a 1x10 header and the sysCONFIG connector is a 2x17 header.
Both the JTAG and the sysCONFIG ports are also provided with loop-through connectors to allow for easy daisy
chaining of multiple boards. With proper jumper selection (see the next section) standard IDC ribbon cable can be
used without the need to swap wires on the cable.
See the Configuring/Programming The Board section of this document for more information on this topic.
The pinouts for these headers are provided in the following tables.
Note: A parallel port ispDOWNLOAD
®
cable is included with each LatticeECP2 Standard Evaluation Board. When
using a parallel port (1x8) ispDOWNLOAD cable, connect pin 1 of the cable to pin 1 of the 1x10 JTAG header. For
more information on the ispDOWNLOAD Cable, see the ispDOWNLOAD Cables Data Sheet available on the Lat-
tice web site at www.latticesemi.com.
Table 1. JTAG Programming Header Pinout
Function
Vcc (3.3V)
TDO
1
TDI
PROGN
1
N/C
TMS
Ground
TCK
1
DONE
INIT Chain
1
1. See section below on jumpers.
J4 (1x10)
1
2
3
4
5
6
7
8
9
10
Table 2. JTAG Loop-Through Header Pinout
Function
N/C
TDO Chain
1
TDI Chain
1
PROGN
N/C
TMS
Ground
TCK
1
DONE
INIT Chain
1
1. See section below on jumpers.
1
J5 (1x10)
1
2
3
4
5
6
7
8
9
10
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Lattice Semiconductor
Table 3. sysCONFIG Header Pinout (J40)
Function
CCLK
BUSY / SISPI
DI/D0
1
D7 / DOUT
1
DONE
D7
D6
D5
D4
D3
D2
D1
D0
CSN
1
CS1N
1
LatticeECP2 Standard Evaluation Board
User’s Guide
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
D6
Function
Ground
Vcc Bank8
INITN
PROGRAMN
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
WRITEN
CFG0
CFG1
CFG2
Vcc Bank8
Ground
1. See section below on jumpers.
Table 4. sysCONFIG Loop-Through Header Pinout (J41)
Function
CCLK
N/C
DOUT / CSSON
N/C
DONE
D7
D6
D5
D4
D3
D2
D1
D0
CSN / N/C
1
CS1N / N/C
N/C
Ground
1
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
N/C
N/C
Function
Ground
INITN
PROGRAMN
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
WRITEN
N/C
N/C
N/C
1. See section below on jumpers.
JTAG and sysCONFIG Jumpers
There are several JTAG and sysCONFIG cabling options that can be selected using jumpers.
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