or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
Introduction_01.3
Lattice Semiconductor
Introduction
LatticeECP/EC Family Data Sheet
Introduction
The LatticeECP/EC family of FPGA devices is optimized to deliver mainstream FPGA features at low cost. For
maximum performance and value, the LatticeECP™ (EConomy Plus) FPGA concept combines an efficient FPGA
fabric with high-speed dedicated functions. Lattice’s first family to implement this approach is the LatticeECP-
DSP™ (EConomy Plus DSP) family, providing dedicated high-performance DSP blocks on-chip. The LatticeEC™
(EConomy) family supports all the general purpose features of LatticeECP devices without dedicated function
blocks to achieve lower cost solutions.
The LatticeECP/EC FPGA fabric, which was designed from the outset with low cost in mind, contains all the critical
FPGA elements: LUT-based logic, distributed and embedded memory, PLLs and support for mainstream I/Os.
Dedicated DDR memory interface logic is also included to support this memory that is becoming increasingly prev-
alent in cost-sensitive applications.
The ispLEVER
®
design tool suite from Lattice allows large complex designs to be efficiently implemented using the
LatticeECP/EC FPGA family. Synthesis library support for LatticeECP/EC is available for popular logic synthesis
tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to
place and route the design in the LatticeECP/EC device. The ispLEVER tool extracts the timing from the routing
and back-annotates it into the design for timing verification.
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP/EC
family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their
design, increasing their productivity.
1-2
LatticeECP/EC Family Data Sheet
Architecture
May 2007
Data Sheet
Architecture Overview
The LatticeECP-DSP and LatticeEC architectures contain an array of logic blocks surrounded by Programmable I/
O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR), as
shown in Figures 2-1 and 2-2. In addition, LatticeECP-DSP supports an additional row of DSP blocks, as shown in
Figure 2-2.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit
without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register func-
tions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks
are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are
arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the out-
side rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every
three rows of PFF blocks there is a row of PFU blocks.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O interfaces. PIO pairs on the left and
right edges of the device can be configured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast
memory blocks. They can be configured as RAM or ROM.
The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in
Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and
route software tool automatically allocates these routing resources.
At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These
PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the
clocks. The LatticeECP/EC architecture provides up to four PLLs per device.
Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG™
port which allows for serial or parallel device configuration. The LatticeECP/EC devices use 1.2V as their core volt-
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
In a project, the author came into contact with such a communication system. The communication architecture of the entire system is roughly as shown in the figure below, a typical one-master-multiple-...
The serial number fixed in the ROM can be read, but the temperature is 0x07ff. The fact that the content in the ROM can be read should indicate that the read and write timing is correct, but the corre...
Power tools have evolved significantly over the past century. Today, they are cordless, lightweight, and battery-powered, making them a great addition to our lives. So what are the factors driving the...
introduction
my country has a vast territory and a large population. The scale of housing construction is huge, and the amount of residential construction is large and wide. It is still on t...[Details]
To differentiate their products in a crowded and competitive market, manufacturers of handheld devices often consider battery life and power management as key selling points for cell phones, PDAs, ...[Details]
July 11, 2012, Beijing - Altera Corporation (NASDAQ: ALTR) today announced the launch of 40-Gbps Ethernet (40GbE) and 100-Gbps Ethernet (100GbE) intellectual property (IP) core products. These core...[Details]
0 Introduction
With the development of society, people pay more and more attention to security work. Monitoring products have been used in various fields instead of being used only in importan...[Details]
I. Introduction
Since RS232 has a short communication distance (only 15 meters according to EAT/TAI-232 standard), and can only perform point-to-point communication, it cannot directly f...[Details]
1. System Structure
This system is a simulation system of indoor air-conditioning temperature/humidity control system. The data acquisition and control center collects temperature/humidity...[Details]
Digital array radar (DAR) uses digital beam forming (DBF) in both receiving and transmitting modes to achieve flexible distribution and reception of RF signal power in the airspace, obtain excellent t...[Details]
In the single-chip microcomputer system, in addition to display devices, sound devices are often used, and the most common sound device is the buzzer. Buzzers are generally used for some low-demand...[Details]
12v Lead Acid batteries used in trucks, cars, RVs and uninterruptible power supplies are usually rated at 12V. This circuit monitors the battery, the charge and discharge curves, gives the cu...[Details]
TC9012F is a universal CMOS large-scale integrated circuit for infrared remote control signal transmission, suitable for remote control of TV, VTR, laser player and other equipment. In the market, ...[Details]
Only a small number of LED manufacturers can produce high-quality LEDs. For applications that are only used for simple indication, low-quality LEDs are sufficient. However, high-quality LEDs must...[Details]
1. Introduction
With the increasing popularity of fully automatic washing machines, consumers have higher and higher requirements for their environmenta...[Details]
introduction
Steam turbines are driven by high-temperature and high-pressure steam generated by boilers to run at high speed. They are key power equipment in thermal power plants. The emergenc...[Details]
Distributed Wireless Communication System (DWCS) uses distributed antennas, distributed processing control, joint signal processing and other technologies to improve the system's spectrum efficie...[Details]
TI Technology Forum
京公网安备 11010802033920号
EEWORLD
