• Seamless migration to next-generation dual-port family
Functional Description
The FLEx18™ family includes 1-Mbit, 2-Mbit, 4-Mbit and
9-Mbit pipelined, synchronous, true dual-port static RAMs that
are high-speed, low-power 3.3V CMOS. Two ports are
provided, permitting independent, simultaneous access to any
location in memory. The result of writing to the same location
by more than one port at the same time is undefined. Registers
on control, address, and data lines allow for minimal set-up
and hold time.
During a Read operation, data is registered for decreased
cycle time. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally (more details to follow). The internal Write pulse width is
independent of the duration of the R/W input signal. The
internal Write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CYD09S18V device in this family has limited features.
Please see Address Counter and Mask Register Operations
on page 5 for details.
Seamless Migration to Next Generation Dual Port Family
Cypress offers a migration path for all devices in this family to
the next-generation devices in the Dual-Port family with a
compatible footprint. Please contact Cypress Sales for more
details.
Table 1. Product Selection Guide
Density
Part Number
Max. Speed (MHz)
Max. Access Time – Clock to Data (ns)
Typical operating current (mA)
Package
1 Mbit
(64K x 18)
CYD01S18V
167
4.0
225
2 Mbit
(128K x 18)
CYD02S18V
167
4.0
225
4 Mbit
(256K x 18)
CYD04S18V
167
4.0
225
9 Mbit
(512K x 18)
CYD09S18V
133
4.7
270
256FBGA
256FBGA
256FBGA
256FBGA
(17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm)
Cypress Semiconductor Corporation
Document #: 38-06077 Rev. *C
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised May 5, 2005
[+] Feedback
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Logic Block Diagram
[1]
FTSEL
L
CONFIG Block
PORTSTD(1:0)
L
CONFIG Block
PORTSTD(1:0)
R
FTSEL
R
DQ (17:0)
L
BE (1:0)
L
CE0
L
CE1
L
OE
L
R/W
L
IO
Control
IO
Control
DQ (17:0)
R
BE (1:0)
R
CE0
R
CE1
R
OE
R
R/W
R
Dual Ported Array
BUSY
L
Arbitration Logic
BUSY
R
A (18:0)
L
CNT/MSK
L
ADS
L
CNTEN
L
CNTRST
L
RET
L
CNTINT
L
C
L
WRP
L
Address &
Counter Logic
Address &
Counter Logic
A (18:0)
R
CNT/MSK
R
ADS
R
CNTEN
R
CNTRST
R
RET
R
CNTINT
R
C
R
WRP
R
Mailboxes
INT
L
INT
R
JTAG
TRST
TMS
TDI
TDO
TCK
READY
L
LowSPD
L
RESET
LOGIC
MRST
READY
R
LowSPD
R
Note:
1. CYD01S18V has 16 address bits, CYD02S18V has 17 address bits, CY04S18V has 18 address bits and CYD09S18V has 19 address bits.
Document #: 38-06077 Rev. *C
Page 2 of 26
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CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Pin Configurations
256-ball BGA Top View
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
NC
2
NC
3
NC
4
DQ17
L
5
DQ16
L
6
DQ13
L
7
DQ12
L
8
DQ9
L
9
DQ9
R
10
DQ12
R
11
DQ13
R
12
DQ16
R
13
DQ17
R
14
NC
15
NC
16
NC
NC
NC
NC
NC
DQ15
L
NC
[2,5]
FTSEL
L
[2,3]
DQ14
L
NC
[2,5]
LowSPD
L
[2,4]
DQ11
L
REV
L
[2,4]
DQ10
L
TRST
[2,5]
VTTL
DQ10
R
DQ11
R
NC
[2,5]
DQ14
R
NC
[2,5]
LowSPD
R
[2,4]
DQ15
R
NC
[2,5]
FTSEL
R
[2,3]
NC
NC
NC
NC
NC
NC
RET
L
[2,3]
INT
L
VREF
L
[2,4]
CE1
L
[9]
MRST
INT
R
VREF
R
[2,4]
CE1
R
[9]
RET
R
[2,3]
NC
NC
A0
L
A1
L
WRP
L
[2,3]
VSS
VTTL
VSS
WRP
R
[2,3]
CE0
R
[10]
A1
R
A0
R
A2
L
A3
L
CE0
L
[10]
CNTINT
L
[11]
VDDIO
L
VDDIO
L
VDDIO
L
VCORE
VCORE
VDDIO
R
VDDIO
R
VDDIO
R
A3
R
A2
R
A4
L
A5
L
NC
VDDIO
L
REV
L
[2,3]
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
R
NC
CNTINT
R
[11]
A5
R
A4
R
A6
L
A7
L
BUSY
L
[2,5]
NC
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
R
NC
BUSY
R
[2,5]
C
R
A7
R
A6
R
A8
L
A9
L
C
L
VTTL
VCORE
VSS
VSS
VSS
VSS
VSS
VSS
VCORE
VTTL
A9
R
A8
R
A10
L
A11
L
VSS
PortSTD1
L
[2,4]
VCORE
VSS
VSS
VSS
VSS
VSS
VSS
VCORE
PortSTD1
R
[2,4]
VSS
A11
R
A10
R
A12
L
A13
L
OE
L
ADS
L
[10]
BE1
L
VDDIO
L
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
R
BE1
R
BE0
R
OE
R
ADS
R
[10]
A13
R
A12
R
A14
L
A16
L
[6]
A18
L
[8]
A15
L
A17
L
[7]
BE0
L
REV
L
[2,4]
VREF
L
VDDIO
L
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
R
A15
R
A17
R
[7]
A14
R
A16
R
[6]
A18
R
[8]
RW
L
CNT/
MSK
L
[9]
CNTEN
L
[10]
VDDIO
L
VDDIO
L
VDDIO
L
REV
L
[2,3]
VCORE
VCORE
VDDIO
R
REV
R
[2,3]
VDDIO
R
VDDIO
R
REV
R
[2,4]
VREF
R
RW
R
CNT/
MSK
R
[9]
CNTEN
R
[10]
NC
[2,4]
PortSTD0
L
[2,4]
READY
L
[2,5]
VTTL
VTTL
READY
R
[2,5]
PortSTD0
R
[2,4]
[2,4]
NC
NC
NC
CNTRST
L
[9]
NC
[2,5]
DQ6
L
NC
[2,5]
DQ5
L
TCK
TMS
TDO
TDI
NC
[2,5]
DQ5
R
NC
[2,5]
DQ6
R
CNTRST
R
[9]
NC
NC
NC
NC
NC
NC
DQ2
L
DQ1
L
DQ1
R
DQ2
R
NC
NC
NC
NC
NC
NC
NC
DQ8
L
DQ7
L
DQ4
L
DQ3
L
DQ0
L
DQ0
R
DQ3
R
DQ4
R
DQ7
R
DQ8
R
NC
NC
NC
Notes:
2. This ball will represent a next generation FLEx18-E Dual-Port feature. For more information about this feature, contact Cypress Sales.
3. Connect this ball to VDDIO. For more information about this next generation FLEx18-E Dual-Port feature contact Cypress Sales.
4. Connect this ball to VSS. For more information about this next generation FLEx18-E Dual-Port feature, contact Cypress Sales.
5. Leave this ball unconnected. For more information about this feature, contact Cypress Sales.
6. Leave this ball unconnected for a 64K x 18.
7. Leave this ball unconnected for a 128K x 18 and 64K x 18.
8. Leave this ball unconnected for a 256K x 18, 128K x 18 and 64K x 18.
9. These balls are not applicable for CYD09S18V device. They need to be tied to VDDIO.
10. These balls are not applicable for CYD09S18V device. They need to be tied to VSS.
11. These balls are not applicable for CYD09S18V device. They need to be no connected.
Document #: 38-06077 Rev. *C
Page 3 of 26
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CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Pin Definitions
Left Port
A
0L
–A
18L
BE
0L
–BE
1L
BUSY
L[2,5]
C
L
CE0
L[10]
CE1
L[9]
DQ
0L
–DQ
17L
OE
L
INT
L
Right Port
A
0R
–A
18R
BE
0R
–BE
1R
BUSY
R[2,5]
C
R
CE0
R[10]
CE1
R[9]
DQ
0R
–DQ
17R
OE
R
INT
R
Address Inputs.
Byte Enable Inputs.
Asserting these signals enables Read and Write operations to
the corresponding bytes of the memory array.
Port Busy Output.
When the collision is detected, a BUSY is asserted.
Input Clock Signal.
Active Low Chip Enable Input.
Active High Chip Enable Input.
Data Bus Input/Output.
Output Enable Input.
This asynchronous signal must be asserted LOW to enable
the DQ data pins during Read operations.
Mailbox Interrupt Flag Output.
The mailbox permits communications between ports.
The upper two memory locations can be used for message passing. INT
L
is asserted
LOW when the right port writes to the mailbox location of the left port, and vice versa.
An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox.
Port Low Speed Select Input.
When operating at less than 100 MHz, the LowSPD
disables the port DLL.
Read/Write Enable Input.
Assert this pin LOW to write to, or HIGH to read from the
dual-port memory array.
Port Ready Output.
This signal will be asserted when a port is ready for normal
operation.
Port Counter/Mask Select Input.
Counter control input.
Port Counter Address Load Strobe Input.
Counter control input.
Port Counter Enable Input.
Counter control input.
Port Counter Reset Input.
Counter control input.
Port Counter Interrupt Output.
This pin is asserted LOW when the unmasked
portion of the counter is incremented to all “1s”.
Port Counter Wrap Input.
After the burst counter reaches the maximum count, if
WRP is low, the unmasked counter bits will be set to 0. If high, the counter will be
loaded with the value stored in the mirror register.
Port Counter Retransmit Input.
Counter control input.
Flow-Through Mode Select Input.
Port External High-Speed IO Reference Input.
Port IO Power Supply.
Reserved pins for future features.
Master Reset Input.
MRST is an asynchronous input signal and affects both ports.
A master reset operation is required at power-up.
JTAG Reset Input.
JTAG Test Mode Select Input.
It controls the advance of JTAG TAP state machine.
State machine transitions occur on the rising edge of TCK.
JTAG Test Data Input.
Data on the TDI input will be shifted serially into selected
registers.
JTAG Test Clock Input.
JTAG Test Data Output.
TDO transitions occur on the falling edge of TCK. TDO is
normally three-stated except when captured data is shifted out of the JTAG TAP.
Description
LowSPD
L[2,4]
LowSPD
R[2,4]
PORTSTD[1:0]
L[2,4]
PORTSTD[1:0]
R[2,4]
Port Address/Control/Data I/O Standard Select Input.
R/W
L
READY
L[2,5]
CNT/MSK
L[9]
ADS
L[10]
CNTEN
L[10]
CNTRST
L[9]
CNTINT
L[11]
WRP
L[2,3]
RET
L[2,3]
FTSEL
L[2,3]
VREF
L[2,4]
VDDIO
L
REV
L[2,4]
MRST
TRST
[2,5]
TMS
TDI
TCK
TDO
R/W
R
READY
R[2,5]
CNT/MSK
R[9]
ADS
R[10]
CNTEN
R[10]
CNTRST
R[9]
CNTINT
R[11]
WRP
R[2,3]
RET
R[2,3]
FTSEL
R[2,3]
VREF
R[2,4]
VDDIO
R
REV
R[2,4]
Document #: 38-06077 Rev. *C
Page 4 of 26
[+] Feedback
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Pin Definitions
(continued)
Left Port
V
SS
V
CORE[12]
V
TTL
Right Port
Ground Inputs.
Core Power Supply.
LVTTL Power Supply.
Description
Master Reset
The FLEx18 family devices undergo a complete reset by
taking its MRST input LOW. The MRST input can switch
asynchronously to the clocks. The MRST initializes the
internal burst counters to zero, and the counter mask registers
to all ones (completely unmasked). The MRST also forces the
Mailbox Interrupt (INT) flags and the Counter Interrupt
(CNTINT) flags HIGH. The MRST must be performed on the
FLEx18 family devices after power-up.
Address Counter and Mask Register
Operations
This section describes the features only apply to 1-Mbit,
2-Mbit, and 4-Mbit devices. It does not apply to a 9-Mbit
device. Each port of these devices has a programmable burst
address counter. The burst counter contains three registers: a
counter register, a mask register, and a mirror register.
[17]
The
counter register
contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
The
mask register
value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only
by the Mask Load and Mask Reset operations, and by the
MRST. The mask register defines the counting range of the
counter register. It divides the counter register into two
regions: zero or more “0s” in the most significant bits define
the masked region, one or more “1s” in the least significant bits
define the unmasked region. Bit 0 may also be “0,” masking
the least significant counter bit and causing the counter to
increment by two instead of one.
The mirror register
is used to reload the counter register on
increment operations (see “retransmit,” below). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and Counter Reset opera-
tions, and by the MRST.
Table 3
summarizes the operation of these registers and the
required input control signals. The MRST control signal is
asynchronous. All the other control signals in
Table 3
(CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the
port’s CLK. All these counter and mask operations are
independent of the port’s chip enable inputs (CE0 and CE1).
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports.
Table
shows the interrupt operation for both ports of CYD09S18V.
The highest memory location, 7FFFF is the mailbox for the
right port and 7FFFE is the mailbox for the left port.
Table
shows that in order to set the INT
R
flag, a Write operation by
the left port to address 7FFFF will assert INT
R
LOW. At least
one byte has to be active for a Write to generate an interrupt.
A valid Read of the 7FFFF location by the right port will reset
INT
R
HIGH. At least one byte has to be active in order for a
Read to reset the interrupt. When one port Writes to the other
port’s mailbox, the INT of the port that the mailbox belongs to
is asserted LOW. The INT is reset when the owner (port) of the
mailbox Reads the contents of the mailbox. The interrupt flag
is set in a flow-thru mode (i.e., it follows the clock edge of the
writing port). Also, the flag is reset in a flow-thru mode (i.e., it
follows the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
Table 2. Interrupt Operation Example
[1, 13, 14, 15, 16]
Left Port
Function
Set Right INT
R
Flag
Reset Right INT
R
Flag
Set Left INT
L
Flag
Reset Left INT
L
Flag
R/W
L
L
X
X
H
CE
L
L
X
X
L
A
0L–18L
7FFFF
X
X
7FFFE
INT
L
X
X
L
H
R/W
R
X
H
L
X
CE
R
X
L
L
X
Right Port
A
0R–18R
X
7FFFF
7FFFE
X
INT
R
L
H
X
X
Notes:
12. This family of Dual-Ports does not use V
CORE
, and these pins are internally NC. The next generation Dual-Port family, the FLEx18-E™, will use V
CORE
of 1.5V
or 1.8V. Please contact local Cypress FAE for more information.
13. CE is internal signal. CE = LOW if CE
0
= LOW and CE
1
= HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK
and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
14. OE is “Don’t Care” for mailbox operation.
15. At least one of BE0, BE1 must be LOW.
16. A18x is a NC for CYD04S18V, therefore the Interrupt Addresses are 3FFFF and 3FFFE. A18x and A17x are NC for CYD02S18V, therefore the Interrupt addresses
are 1FFFF and 1FFFE; A18x, A17x and A16x are NC for CYD01S18V, therefore the Interrupt Addresses are FFFF and FFFE.
17. This section describes the CYD04S18V, CYD02S18V, CYD01S18V 18, 17, and 16 address bits.
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