CXA2503AR
Decoder/Driver/Timing Generator for Color LCD Panels
Description
The CXA2503AR is an IC designed exclusively to
drive color LCD panels LCX005BK/BKB and
LCX009AK/AKB.
This IC greatly reduces the number of circuits and
parts required to drive LCD panels by incorporating
RGB decoder functions for video signals, driver
functions, and a timing generator for driving panels
onto a single chip.
This chip has a built-in serial interface circuit and
electronic attenuators which allow various mode
settings and adjustments to be performed through
direct control from an external microcomputer, etc.
Features
•
Color LCD panels LCX005BK/BKB and LCX009AK/
AKB driver
•
Supports NTSC and PAL systems
•
Supports 16:9 wide display
•
Supports composite inputs, Y/C inputs and Y/color
difference inputs
•
Serial interface circuit
•
Electronic attenuators (D/A converter)
•
BPF, trap and delay line
•
Sharpness function
•
2-point
γ
correction circuit
•
R, G, B signal delay time adjustment circuit
•
Polarity inversion circuit (line inverted mode)
•
Supports external RGB input
•
Supports AC drive for LCD panel during no signal
Applications
•
LCD viewfinders
•
Compact liquid crystal projectors
•
Compact LCD monitors
Structure
Bipolar CMOS IC
Absolute Maximum Ratings
(Ta = 25°C)
6
•
Supply voltage V
CC
1 – GND1, 3
V
CC
2 – GND2
14
V
DD
1 – V
SS
1
4.5
V
DD
2 – V
SS
2
•
Analog input pin voltage VINA
•
•
•
•
4.5
–0.3 to V
CC
1
64 pin LQFP (Plastic)
V
V
V
V
V
Digital input pin voltage VIND –0.3 to V
DD
1 + 0.3 V
Operating temperature Topr
–15 to +75 °C
Storage temperature
Tstg
–40 to +125 °C
Allowable power dissipation
P
D
(Ta
≤
75°C) 350mW
Note)
Operating conditions
Supply voltage V
CC
1 – GND1, 3 4.25 to 5.25
V
CC
2 – GND2
11.0 to 13.5
V
DD
1 – V
SS
1
2.7 to 3.6
V
DD
2 – V
SS
2
2.7 to 3.6
Note)
With substrate
Size: 114.3
×
76.1
×
1.5mm
Material: Glass fabric base epoxy
V
V
V
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97910-PS
CXA2503AR
Block Diagram
SIG.CENTER
G OUT
R OUT
TEST4
TEST3
TEST2
B OUT
GND2
LOAD
DATA
V
CC
2
FB R
RGT
48
47
+12V
46
45
44
43
42
41
40
GND2
39
38
37
36
35
34
33
buf
V
CC
1 49 +4.5V
buf
buf
SEREAL
BAS I/F
V
SS
2 32 V
SS
2
B-Y IN 50
CLAMP
R-Y IN 51
EXT COLOR
& BALANCE
C OUT 52
INT/EXT
R-BRT
BLK LIM 53
APC
B-BRT
APC 54
VXO
HUE
PS
LPF
BRT
MATRIX
VXO OUT 55
HUE
COLOR
CONTRAST
CNTRAST
COLOR CONT
V REG 57
REG.
ACC DET
KILLER
START UP 58
BPF
PIC CONT
C IN 59
ACC AMP
HAFC
PLL-COUNTER
& DECODER
HD
EXT SW
RGB
γ
-2
S/H
γ
-1
GAMMA
D/A
BRIGHT
PALSW
SUB-
BRIGHT
VWIN
VPAL
COLOR
HUE
PAL ID
PAL
SW
SCLK
FB G
FB B
31 VD2
DEMOD
POL SW
VGATE
WIDE
VTST
30 VD1
FRP
29 EN
28 VCK1
27 VCK2
26 VST
VXO IN 56
25 TEST1
24 FLD IN
23 FLD OUT
22 HD
F0 ADJ 60
FILT ADJ
CLP
BGP
SBLK
V-SEP
CLAMP
TRAP
DL 1
HCNT
H-PULSE
21 HCK1
GND3 61
GND3
Y IN 62
20 HCK2
HGATE
H-SKEW DET
SYNC SEP
19 HST
PD
18 CLR
PIC 63
TEST0 64
H. FILTER
PLL
+3V 17 V
DD
2
VCO ADJ
GND1
1
2
3
4
5
6
7
8
9
10
11
12
V
SS
1
13
14
15
+3V
16
PWRST
H.FIL OUT
VCO ADJ
RPD
SYNC IN
EXT B
GND1
EXT G
TRAP
EXT R
VD IN
S.SEP IN
–2–
V
DD
1
V
SS
1
CKO
CKI
CXA2503AR
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Symbol
PWRST
VD IN
TRAP
GND1
SYNC IN
H.FIL OUT
S.SEP IN
EXT R
EXT G
EXT B
VCO ADJ
RPD
V
SS
1
CKI
CKO
V
DD
1
V
DD
2
CLR
HST
HCK2
HCK1
HD
FLD OUT
FLD IN
TEST1
VST
VCK2
VCK1
EN
VD1
VD2
V
SS
2
O
O
O
O
O
O
O
O
O
O
O
O
I
I
O
I
O
I
I
I
I
O
O
I/O
—
I
System reset
External vertical sync input
External trap connection
Analog 4.5V GND
Video input for sync separation
Video output for sync input
Sync separation circuit input
External digital input R
External digital input G
External digital input B
VCO adjustment voltage output
Phase comparator output
Digital 3V GND for oscillation cell
Oscillation cell input
Oscillation cell output
Digital 3V power supply for oscillation cell
Digital 3V power supply
CLR pulse output
H start pulse output
H clock pulse 2 output
H clock pulse 1 output
HD pulse output
Field identification output
Field identification input
Test (Leave this pin open.)
V start pulse output
V clock pulse 2 output
V clock pulse 1 output
EN pulse output
VD1 pulse output
VD2 pulse output
Digital 3V GND
Description
Input pin for
open status
–3–
CXA2503AR
Pin
No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Symbol
SCLK
DATA
LOAD
TEST2
TEST3
TEST4
RGT
GND2
B OUT
FB B
G OUT
FB G
R OUT
FB R
V
CC
2
SIG.CENTER
V
CC
1
B-Y IN
R-Y IN
C OUT
BLK LIM
APC
VXO OUT
VXO IN
V REG
START UP
C IN
F0 ADJ
GND3
Y IN
PIC
TEST0
I/O
I
I
I
Serial interface clock input
Serial interface data input
Serial interface load input
Test (Leave this pin open.)
Test (Leave this pin open.)
Test (Leave this pin open.)
I
Description
Input pin for
open status
H
H
H
Switches between Normal scan (H) and Reverse scan (L)
Analog 12V GND
H
O
O
O
O
O
O
B output
B signal DC voltage feedback circuit capacitor connection
G output
G signal DC voltage feedback circuit capacitor connection
R output
R signal DC voltage feedback circuit capacitor connection
Analog 12V power supply
I
RGB output DC voltage adjustment
Analog 4.5V power supply
I
I
O
I
O
O
I
O
O
I
O
B-Y demodulator input (or B-Y color difference signal input)
R-Y demodulator input (or R-Y color difference signal input)
Chroma signal output
Black peak limiter level adjustment
APC detective filter connection
VXO output
VXO input
Constant voltage capacitor connection
Startup time constant connection
Chroma signal input
Internal filter adjusting resistor connection
Analog 4.5V GND
I
I
I
Y signal input
Y signal frequency response adjustment
Test (Leave this pin open.)
(H: Pull up)
–4–
CXA2503AR
Analog Block Pin Description
Pin
No.
Symbol
Pin voltage
V
DD
2
2µA
1
Equivalent circuit
Description
1
PWRST
—
1k
TG block system reset pin.
The system is reset when this
pin is connected to GND.
Connect a capacitor between
this pin and GND.
GND1
V
DD
2
50k
50k
2
50k
GND1
2
VDIN
—
External vertical sync signal
input.
V
CC
1
70µA
1k
300
3
130µA
GND1
3
TRAP
2.2V
External trap connection.
Connect the trap between this
pin and GND to remove the
chroma component.
V
DD
1
1k
5
SYNC IN
1.5V
5
1k
30µA
GND1
2.1V
Sync input.
Normally inputs the Y signal.
The standard signal input level
is 0.5Vp-p (100% white level
from the sync tip).
V
DD
2
20k
6
6
H.FIL OUT
2.5V
Outputs the video signal for
input to the sync separation
circuit.
20k
GND1
–5–
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