HV5222
32-Channel Serial to Parallel Converter
With Open Drain Outputs
Features
►
Processed with HVCMOS
®
technology
►
Output voltages to 225V using a ramped supply
voltage
►
SINK current minimum 100mA
►
Shift register speed 8.0MHz
►
Strobe and enable inputs
►
CMOS compatible inputs
►
Forward and reverse shifting options
►
Hi-Rel processing available
General Description
The HV5222 is a low voltage serial to high voltage parallel
converter with open drain outputs. This device has been designed
for use as a driver for AC electroluminescent displays.They can
also be used in any application requiring multiple output high
voltage current sinking capabilities such as driving inkjet and
electrostatic print heads, plasma panels, vacuum fluorescent, or
large matrix LCD displays.
This device consists of a 32-bit shift register and control logic to
perform the Output Enable and all-on functions. Data is shifted
through the shift register on the high to low transition of the
clock. The HV5222 shifts in the clockwise direction when viewed
from the top of the package. A data output buffer is provided for
cascading devices. This output reflects the current status of the
last bit of the shift register. Operation of the shift register is not
affected by the OE(Output Enable) or the STR (Strobe) inputs.
The HV5222 has been designed to be used in systems which
either switch off the high voltage supply before changing the state
of the high voltage outputs or which limit the current through each
output.
Functional Block Diagram
Strobe
Output Enable
Data Input
HV
OUT
2
Clock
•
•
•
28 Additional
Outputs
•
•
•
HV
OUT
31
HV
OUT
1
32 bit
Static Shift
Register
HV
OUT
32
Data Out
HV5222
Ordering Information
Package Options
Device
44-Lead Quad
Cerpac Chip Carrier
.650x.650in body
.190in height (max)
.050in pitch
10.00x10.00mm body
2.45mm height (max)
0.80mm pitch
44-Lead Quad
Plastic Gullwing
44-Lead Quad
Plastic Chip Carrier
.653x.653in body
.180in height (max)
.050in pitch
HV5222
HV5222DJ*
HV5222PG-G
HV5222PJ-G
-G indicates package is RoHS compliant (‘Green’)
* Hi-Rel processing available
Pin Configurations
6
1 44
40
Absolute Maximum Ratings
Parameter
Supply voltage, V
DD
Supply voltage, V
PP
Logic input levels
Ground current
1
Continuous total power dissipation
2
Plastic
Ceramic
Operating temperature range
Plastic
Ceramic
Storage temperature range
Lead temperature
3
Value
-0.5V to +15V
-0.5V to +250V
-0.5V to V
DD
+0.5V
1.5A
1200W
1500W
-40
O
C to +85
O
C
-55
O
C to +125
O
C
-65
O
C to +150
O
C
260
O
C
44-Lead Quad Cerpac Chip Carrier (DJ)
44
1
44-Lead Quad Plastic Gullwing (PG)
6
1 44
40
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
Notes:
1. Duty cycle is limited by the total power dissipated in the package.
2. For operation above 25°C ambient derate linearly to maximum
operatingtemperature at 20mW/°C for plastic and at 15mW/°C for
ceramic.
3. 1.6mm (1/16 inch) from case for 10 seconds
44-Lead Quad Plastic Chip Carrier (PJ)
Product Marking
Top Marking
HV5222DJ
YYWW
Top Marking
Top Marking
LLLLLLLLLL
Bottom Marking
CCCCCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
*May be part of top marking
YY W W
HV5222PG
L LLL LL L L L
Bottom Marking
CCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
HV5222PJ
YYWW
LLLLLLLLLL
Bottom Marking
CCCCCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
44-Lead Quad Plastic Chip Carrier
(DJ)
44-Lead Quad Plastic Gullwing
(PG)
2
44-Lead Quad Plastic Chip Carrier
(PJ)
HV5222
Recommended Operating Conditions
Sym
V
DD
HV
OUT
V
IH
V
IL
f
CLK
T
A
Parameter
Logic voltage supply
High voltage output
High-level input voltage
Low-level input voltage
Clock frequency
Operating free-air temperature
Plastic
Ceramic
Min
10.8
-0.3
V
DD
-2.0
0
-
-40
-55
Typ
12
-
-
-
-
-
-
Max
13.2
225
V
DD
2.0
8.0
+85
+125
Units
V
V
V
V
MHz
O
C
Power-Up Sequence
Power-up sequence should be the following:
1. Connect ground
2. Apply V
DD
3. Set all inputs to a known state
Power-down sequence should be the reverse of the above.
Electrical Characteristics
(Over recommended operating conditions unless otherwise specified)
DC Characteristics
Sym
I
DD
I
DDQ
I
O(OFF)
I
IH
I
IL
V
OH
V
OL
V
OC
Parameter
V
DD
supply current
Quiescent V
DD
supply current
Off-state output current
High level logic input current
Low level logic input current
High level output data out
Low level output voltage
HV
OUT
clamp voltage
DD
Min
-
-
-
-
-
V
DD
-1.0V
HV
OUT
Data out
-
-
-
Max
15
100
10
1.0
-1.0
-
15
1.0
-1.5
Units
mA
µA
µA
µA
µA
V
V
V
Conditions
f
CLK
= 8.0MHz, F
DATA
= 4.0MHz
All V
IN
= 0V
All outputs high, all SWS parallel
V
IH
= 12V
V
IL
= 0
I
DOUT
= -100µA
I
HVOUT
= +100mA
I
DOUT
= +100µA
I
OL
= -100mA
AC Characteristics
(V
Sym
f
CLK
t
W
t
SU
t
H
t
ON
t
DHL
t
DLH
Parameter
= 12V, T
A
= 25°C)
Min
-
62
25
10
-
-
-
Max
8.0
-
-
-
500
100
100
Units
MHz
ns
ns
ns
ns
ns
ns
Conditions
---
---
---
---
R
L
= 2.0KΩ to 200V
C
L
= 15pF
C
L
= 15pF
Clock frequency
Clock width, high or low
Data setup time before CLK falls
Data hold time after CLK falls
Turn-on time, HV
OUT
from strobe
Data output delay after H to L CLK
Data output delay after L to H CLK
3
HV5222
Input and Output Equivalent Circuits
VDD
VDD
HV
OUT
Data Out
Input
HV
IN
GND
GND
Logic Inputs
GND
Logic Data Output
High Voltage Outputs
Switching Waveforms
Data
In
t
SU
12V
Data Valid 1
t
H
50%
0V
12V
0V
Clock
50%
50%
t
WH
t
WL
50%
Data
Out
t
DHL
Data
Out
t
DLH
Strobe
50%
t
ON
HV
OUT
15V
Function Table
Inputs
Function
All on
All off
Load S/R
Output Enable
Data
X
X
H OR L
X
CLK
X
X
↓
H OR L
OE
X
L
L
H
Strobe
L
H
H
H
Shift Reg
1 2...32
●
●
●...●
●...●
Outputs
HV Outputs
1 2...32
ON ON...ON
OFF OFF...OFF
OFF OFF...OFF
ON or OFF ●...●
Data
Out
●
●
-
●
H or L ●...●
H or L ●...●
Notes:
H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition
●
= dependent on previous stage’s state before the last CLK: High-to-low transition
4
HV5222
44-Lead PQFP Pin Assignment (PG)
HV5222PG
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Output enable input.
28
OE
When OE is LOW, all HV outputs are forced into a LOW state, regardless of data in
each channel. When OE is HIGH, all HV outputs reflect data latched.
Data shift register clock.
Input are shifted into the shift register on the positive edge of the clock.
Logic and high voltage ground.
Low voltage logic power rail.
Strobe.
Serial data input
Data needs to be present before each rising edge of the clock.
N/C
No connect.
Function
HV
OUT
22
HV
OUT
21
HV
OUT
20
HV
OUT
19
HV
OUT
18
HV
OUT
17
HV
OUT
16
HV
OUT
15
HV
OUT
14
HV
OUT
13
HV
OUT
12
HV
OUT
11
HV
OUT
10
HV
OUT
9
HV
OUT
8
HV
OUT
7
HV
OUT
6
HV
OUT
5
HV
OUT
4
HV
OUT
3
HV
OUT
2
HV
OUT
1
DATA OUT
Serial data output
Data output for cascading to the data input of the next device.
High voltage outputs.
Description
29
30
31
32
33
CLK
GND
VDD
STR
DATA IN
5
京公网安备 11010802033920号
EEWORLD
