AND-OR-Invert Gate, TTL, CDIP14,
| Parameter Name | Attribute value |
| Is it lead-free? | Contains lead |
| Is it Rohs certified? | incompatible |
| Maker | Fairchild |
| Reach Compliance Code | unknown |
| JESD-30 code | R-XDIP-T14 |
| JESD-609 code | e0 |
| Logic integrated circuit type | AND-OR-INVERT GATE |
| Humidity sensitivity level | 2A |
| Number of terminals | 14 |
| Maximum operating temperature | 125 °C |
| Minimum operating temperature | -55 °C |
| Package body material | CERAMIC |
| encapsulated code | DIP |
| Encapsulate equivalent code | DIP14,.3 |
| Package shape | RECTANGULAR |
| Package form | IN-LINE |
| Peak Reflow Temperature (Celsius) | 250 |
| power supply | 5 V |
| Certification status | Not Qualified |
| Schmitt trigger | NO |
| Nominal supply voltage (Vsup) | 5 V |
| surface mount | NO |
| technology | TTL |
| Temperature level | MILITARY |
| Terminal surface | Tin/Lead (Sn/Pb) |
| Terminal form | THROUGH-HOLE |
| Terminal pitch | 2.54 mm |
| Terminal location | DUAL |
| Maximum time at peak reflow temperature | 30 |
| Base Number Matches | 1 |
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