CXD1961Q
DVB-S Front-end IC (QPSK demodulator + FEC)
Description
The CXD1961Q is a single chip DVB Satellite
Broadcasting Front-end IC, including dual ADC for
analog I/O inputs, QPSK demodulator, Viterbi
decoder, de-interleaver, Reed-Solomon decoder
and Energy Dispersal descrambler.
It is suitable for use in a DVB Integrated Receiver
Decoder.
Features
•
Dual 6 bit A/D converters
•
QPSK demodulator
Multi-symbol rate operation
Nyquist roll off filter (α = 0.35)
Clock recovery circuit
Carrier recovery circuit
•
AGC control circuit
Viterbi decoder
Constraint length K =7
Punctured rate R = 1/2 –7/8
Truncation length 144
Punctured rate search function
BER monitor
De-interleaver
Packet synchronization
Convolutional de-interleaver
Reed-Solomon decoder (204, 188)
Energy dispersal descrambler
CPU interface
l
2
C bus interface/8 bit CPU bus
TTL interface level (5V input capability)
JTAG(IEEE std 1149.1–1990) test mode
Package : QFP-100pin
Single +3.3V Power Supply
Symbol rate max:32MSPS min:TBD
Power consumption TBD
0.4um CMOS Technology
Preliminary
100 pin QFP (Plastic)
Absolute Maximum Ratings
(Ta=25°C, GND=0V)
•
Supply voltage
V
DD
–0.5 to 4.6
V
• Input voltage
• Output voltage
• I/O voltage
V
IN
–0.5 to V
DD
+0.5
V
OUT
–0.5 to V
DD
+0.5
V
I/O
–0.5 to V
DD
+0.5
V
CPUIF
–0.5 to 5.5
0 to +75
–55 to +150
V
V
V
V
°C
°C
• CPU I/F pin
•
Operating temperature Topr
•
Storage temperature Tstg
•
DC Recommended Operating Conditions
(Ta=0°C to 75°C, GND=0 V)
•
Supply voltage
V
DD
3.15 to 3.45
V
• Input Hi-level
V
IH
V
DD
–0.7 to V
DD
+0.5 V
• Input Lo-level
V
IL
0.3 to V
DD
+0.2 V
•
•
•
•
•
•
•
•
•
Applications
•
DVB-S Set Top Box (Satellite)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
PE96417-TE
CXD1961Q
Block Diagram
100 99 98
97 96 95
94 93 92
91 90 89
88 87
86 85 84
83 82 81
80
Analog I/Q
Sampling
Clock
2ch ADC
79
VCO
78
77
PLL
76
75
74
Digital
Filter
QPSK
Demodulator
73
72
71
70
NCO
Viterbi Decoder
69
68
67
66
65
64
De-interleaver
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Oscillator
JTAG
18
19
20
21
22
23
24
25
26
27
28
29
30
63
62
61
60
Reed-Solomon
Decoder
CPU I/F
l
2
C
bus
59
58
57
56
Energy Dispersal
55
54
53
8bit CPU bus
52
51
Decoded
data & clock
31 32
33 34 35
36 37 38 39
40 41 42
43 44 45 46
47 48 49 50
Typical Application Block Diagram
Amp
SAW
I/Q
Detector
LPF
SONY
CXD1961Q
LPF
VCO
PLL
QPSK+FEC
Data
LNB
Clock
90°
Reference
OSC
LPF
Crystal
Micro Controller
—2—
CXD1961Q
Pin Configuration
OPOUT
VCOEN
CPOUT
OPX IN
TEST7
TEST6
RW
V
DD
11
V
SS
11
AVD0
AVD1
AVS1
RB1
RT0
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
AVS0
1
RB0
2
V
DD
0
3
V
SS
0
4
CPUSEL
5
PLLSEL
6
TEST1
7
TEST2
8
TEST3
9
V
DD
1 10
V
SS
1 11
SDATA 12
SCLK 13
SEN 14
V
DD
2 15
V
SS
2 16
TCK 17
TMS 18
TDO 19
TDI 20
CK8OUT 21
RESET 22
TE 23
V
DD
3 24
V
SS
3 25
PKTCLK 26
BYTCLK 27
PKTERR 28
DATA0 29
DATA1 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80 V
DD
10
79 CR7
78 CR6
77 CR5
76 CR4
75 V
SS
9
74 V
DD
9
72 CR3
73 CR2
71 CR1
70 CR0
69 CKV
68 AGCPWM
67 V
SS
8
66 V
DD
8
65 TEST5
64 TEST4
63 XI
62 XO
61 V
SS
7
60 V
DD
7
59 SDA
58 SCL
57 A
DD
3
56 A
DD
2
55 A
DD
1
54 V
SS
6
53 V
DD
6
52 A
DD
0
51 CS
RT1
QIN
IIN
DATA7
DATA2
DATA3
V
DD
5
DATA4
V
SS
5
V
DD
4
V
SS
4
DATA5
DATA6
—3—
DS
D0
D1
D2
D3
D4
D5
D6
D7
V
SS
10
VCOC
AVD2
AVS2
CXD1961Q
Pin Description
No.
1
2
3
4
5
6
7–9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29–33
34
35
36–38
39–43
44
45
46–48
49
50
51
52
53
54
Symbol
AVS0
RB0
V
DD
0
V
SS
0
CPUSEL
PLLSEL
TEST1–3
V
DD
1
V
SS
1
SDATA
SCLK
SEN
V
DD
2
V
SS
2
TCK
TMS
TDO
TDI
CK8OUT
RESET
TE
V
DD
3
V
SS
3
PKTCLK
BYTCLK
PKTERR
DATA0–4
V
DD
4
V
SS
4
DATA5–7
D0–D4
V
DD
5
V
SS
5
D5–D7
RW
DS
CS
A
DD
0
V
DD
6
V
SS
6
I/O
—
—
—
—
I
I
I
—
—
O
O
O
—
—
I
I
O
I
O
I
I
—
—
O
O
O
O
—
—
O
I/O
—
—
I/O
I
I
I
I
—
—
Description
Analog Ground
ADC0 bottom reference voltage
Digital Power Supply (+3.3 V)
Digital Ground
CPU interface select (L : I
2
C bus)
Connect Digital Ground
Test input (connect Digital Ground)
Digital Power Supply (+3.3 V)
Digital Ground
SONY internal use
SONY internal use
SONY internal use
Digital Power Supply (+3.3 V)
Digital Ground
JTAG test clock
JTAG test mode select
JTAG test data output
JTAG test data input
Divide by 8 clock of Crystal clock
Reset input (L : reset)
Test Enable (H : test enable)
Digital Power Supply (+3.3 V)
Digital Ground
R/S Packet clock
R/S Byte clock
R/S uncorrectable Packet flag
R/S data output (DATA0 : LSB)
Digital Power Supply (+3.3 V)
Digital Ground
R/S data output (DATA7 : MSB)
8 bit CPU bus data I/O (D0 : LSB)
Digital Power Supply (+3.3 V)
Digital Ground
8 bit CPU bus data I/O (D7 : MSB)
8 bit CPU bus Read/Write (H : Read)
8 bit CPU bus Data strobe
8 bit CPU bus Chip Select
8 bit CPU bus Address0 (LSB)
Digital Power Supply (+3.3 V)
Digital Ground
—4—
CXD1961Q
No.
55–57
58
59
60
61
62
63
64, 65
66
67
68
69
70–73
74
75
76–79
80
81
82, 83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
ADD1–3
SCL
SDA
V
DD
7
V
SS
7
XO
XI
TEST4, 5
V
DD
8
V
SS
8
AGCPWM
CKV
CR0–3
V
DD
9
V
SS
9
CR4–7
V
DD
10
V
SS
10
TEST6, 7
V
DD
11
V
SS
11
CPOUT
AVD2
VCOC
OPXIN
OPOUT
AVS2
VCOEN
RT1
AVD1
QIN
AVS1
RB1
RT0
AVD0
IIN
I/O
I
I
I/O
—
—
O
I
O
—
—
O
O
O
—
—
O
—
—
O
—
—
O
—
I
I
O
—
I
—
—
I
—
—
—
—
I
Description
8 bit CPU bus Address1–3 (ADD3 : MSB)
I
2
C bus serial clock
I
2
C bus serial data
Digital Power Supply (+3.3 V)
Digital Ground
Oscillator output (for Crystal)
Oscillator input (for Crystal)
Test output (V
SS
level)
Digital Power Supply (+3.3 V)
Digital Ground
PWM output for AGC
Sampling Clock monitor output
Clock Recovery data 0–3 (CR0 : LSB)
Digital Power Supply (+3.3 V)
Digital Ground
Clock Recovery data 4–7 (CR7 : MSB)
Digital Power Supply (+3.3 V)
Digital Ground
Test output (V
SS
level)
Digital Power Supply (+3.3 V)
Digital Ground
PLL Charge pump output
Analog Power Supply (+3.3 V)
VCO control voltage input
Embedded OP-Amp Negative input
Embedded OP-Amp output
Analog Ground
VCO enable (H : enable)
ADC1 top reference voltage
Analog Power Supply (+3.3 V)
Analog Q input (ADC1 input)
Analog Ground
ADC1 bottom reference voltage
ADC0 top reference voltage
Analog Power Supply (+3.3 V)
Analog input (ADC0 input)
Note)
Apply 0.1 µF capacitor to every power supply terminal.
Apply 0.1µF capacitor to RB0, RT0, RB1, RT1 for stable A to D conversion.
—5—
Electronics Design Contest
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