CXD2548R
CD Digital Signal Processor with Built-in Digital Servo and DAC
Description
The CXD2548R is a digital signal processor LSI for
CD players. This LSI incorporates a digital servo,
digital filter, zero detection circuit, 1-bit DAC and
analog low-pass filter on a single chip.
Features
•
All digital signal processing during playback is
performed with a single chip
•
Highly integrated mounting possible due to a built-
in RAM
Digital Signal Processor (DSP) Block
•
Playback mode which supports CAV (Constant
Angular Velocity)
•
Frame jitter free
•
0.5
×
to 2.5
×
continuous playback possible
•
Allows relative rotational velocity readout
•
Supports spindle external control
• Wide capture range playback mode
•
Spindle rotational velocity following method
•
Supports normal-speed, double-speed playback
•
16K RAM
•
EFM data demodulation
•
Enhanced EFM frame sync signal protection
•
SEC strategy-based error correction
•
Subcode demodulation and Sub Q data error
detection
•
Digital spindle servo
•
16-bit traverse counter
•
Asymmetry compensation circuit
•
CPU interface on serial bus
•
Error correction monitor signal, etc. output from a
new CPU interface
•
Servo auto sequencer
•
Digital audio interface outputs
•
Digital level meter, peak meter
Digital Servo (DSSP) Block
•
Microcomputer software-based flexible servo control
•
Offset cancel function for servo error signal
•
Auto gain control function for servo loop
•
E:F balance, focus bias adjustment functions
•
Surf jump function supporting micro two-axis
Digital Filter, DAC and Analog Low-Pass Filter Blocks
•
Digital de-emphasis
•
Digital attenuation
•
Zero detection function
•
8Fs oversampling digital filter
•
S/N: 100dB or more (master clock: 384Fs, typ.)
•
THD + N: 0.007% or more (master clock: 384Fs,
typ.)
•
Rejection band attenuation: –60dB or more
Applications
CD players
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
–0.3 to +7.0
V
•
Supply voltage
V
DD
•
Input voltage
V
I
–0.3 to +7.0
V
(V
SS
– 0.3V to V
DD
+ 0.3)
•
Output voltage
V
O
–0.3 to +7.0
V
•
Storage temperature Tstg
–40 to +125 °C
•
Supply voltage difference
V
SS
– AV
SS
–0.3 to +0.3
V
V
DD
– AV
DD
–0.3 to +0.3
V
Recommended Operating Conditions
–3.4 to +5.25 V
•
Supply voltage
V
DD
Note)
•
Operating temperature Topr
–20 to +75 °C
Note)
The V
DD
(Min.) for the CXD2548R varies
according to the playback speed selection.
V
DD
(min.) [V]
Playback
speed
CD-DSP block DAC block DSSP block
2
×
1
×
1
×∗
1
3.4V
3.4V
3.4V
4.5V
3.4V
3.4V
3.4V
3.4V
112 pin LQFP (Plastic)
∗
1
When the internal operation of the CD-DSP side
is set to double-speed mode and the crystal
oscillation frequency is halved, normal-speed
playback results.
I/O Capacitance
•
Input pin
•
Output pin
C
I
C
O
12 (Max.)
12 (Max.)
pF
pF
Note)
Measurement conditions V
DD
= V
I
= 0V
f
M
= 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96404-PS
CXD2548R
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
SYSM
RMUT1
LMUT2
CKOUT
V
DD
0
SBSO
EXCK
SQCK
SQSO
SENS
SCLK
DATA
XLAT
CLOK
XRST
ACDT
PWMI
XLON
SPOA
WFCK
GTOP
XUGF
XPCK
GFS
RFCK
C2PO
XROF
SCOR
MNT0
MNT1
MNT3
Vss1
DOUT
ATSK
MIRR
DFCT
O
I
O
O
1, 0
1, 0
1, 0
O
I
I
O
O
I
I
I
I
I
O
I
O
I
O
O
O
O
O
O
O
O
O
O
O
O
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
I
O
O
O
1, 0
1, 0
1, 0
I/O
Description
System mute input. (high = on, low = off)
R ch zero detection output. (high = on, low = off)
L ch zero detection output. (high = on, low = off)
DAC master clock frequency division output. Either the clock input from
XTAI
×
1,
×
1/2 or
×
1/4, or low output is selected and output.
Digital power supply.
Sub P to W serial output.
SBSO readout clock input.
SQSO readout clock input.
Sub Q 80-bit and PCM peak and level data 16-bit output.
SENS output to CPU.
SENS serial data readout clock input.
Serial data input from CPU.
Latch input from CPU. Serial data is latched at the falling edge.
Serial data transfer clock input from CPU.
System reset. Reset when low.
Normally not used. Leave open.
Spindle motor external control input.
Microcomputer extension interface (output).
Microcomputer extension interface (input A).
WFCK (Write Flame Clock) output.
GTOP output.
XUGF output.
XPLCK output.
GFS output.
RFCK output.
C2PO output.
XRAOF output.
Outputs a high signal when either subcode sync S0 or S1 is detected.
MNT0 output.
MNT1 output.
MNT3 output.
Digital GND.
Digital Out output pin.
Anti-shock pin.
Mirror signal output.
Defect signal output.
–4–
CXD2548R
Pin
No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
Symbol
FOK
V
DD
1
VPCO1
VPCO2
VCKI
V16M
VCTL
PCO
FILO
FILI
AVss4
CLTV
AV
DD
4
RFAC
BIAS
ASYI
ASYO
VC
FE
SE
TE
CE
RFDC
RFC
ADIO
AVss3
IGEN
AV
DD
3
TES2
TES3
Vss2
TEST
SFDR
SRDR
TFDR
TRDR
FFDR
I
O
O
O
O
O
I
I
I
I
I
I
O
I
I
I
I
I
I
I
O
I
O
O
I
O
I
O
O
I
O
I/O
1, 0
Focus OK signal output.
Digital power supply.
1, Z, 0
1, Z, 0
Description
Wide-band EFM PLL charge pump output.
Wide-band EFM PLL VCO2 charge pump output.
Wide-band EFM PLL VCO2 oscillation input.
1, 0
Wide-band EFM PLL VCO2 oscillation output.
Wide-band EFM PLL VCO2 control input.
1, Z, 0
Analog
Master PLL charge pump output.
Master PLL filter output (slave = digital PLL).
Master PLL filter input.
Analog GND.
Master VCO control voltage input.
Analog power supply.
EFM signal input.
Asymmetry circuit constant current input.
Asymmetry comparator voltage input.
1, 0
EFM full-swing output (low = V
SS
, high = V
DD
).
Center voltage input.
Focus error signal input.
Sled error signal input.
Tracking error signal input.
Center error signal input.
RF signal input. Input range: 2.15 to 5.0V. (when DV
DD
= AV
DD
= 5.0V)
Connects an RF signal LPF time-constant capacitor.
Operational amplifier output.
Analog GND.
Connects an operational amplifier current source reference resistor.
Analog power supply.
Test pin. Normally fixed to low.
Test pin. Normally fixed to low.
Digital GND.
Test pin. Normally fixed to low.
1, 0
1, 0
1, 0
1, 0
1, 0
Sled drive output.
Sled drive output.
Tracking drive output.
Tracking drive output.
Focus drive output.
–5–
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