CXD2587Q
CD Digital Signal Processor with Built-in Digital Servo and DAC
Description
The CXD2587Q is a digital signal processor LSI for
CD players. This LSI incorporates a digital servo,
digital filter, zero detection circuit, 1-bit DAC and
analog low-pass filter.
Features
Digital Signal Processor (DSP) Block
•
1×, 2×, 4× speed playback supported
•
16K-RAM
•
EFM data demodulation
•
Enhanced EFM frame sync signal protection
•
SEC strategy-based error correction
•
Subcode demodulation and Sub Q data error
detection
•
Digital spindle servo
•
16-bit traverse counter
•
Asymmetry compensation circuit
•
CPU interface on serial bus
•
Error correction monitor signal, etc. output from a
new CPU interface
•
Servo auto sequencer
•
Digital audio interface outputs
•
Digital level meter, peak meter
•
CD TEXT data demodulation
Digital Servo (DSSP) Block
•
Microcomputer software-based flexible servo control
•
Offset cancel function for servo error signal
•
Auto gain control function for servo loop
•
E:F balance, focus bias adjustment function
•
Surf jump function supporting micro two-axis
Digital Filter, DAC and Analog Low-pass Filter Blocks
•
DBB (digital bass boost) function
•
Double-speed playback supported
•
Digital de-emphasis
•
Digital attenuation
•
8Fs oversampling filter
•
S/N: 100dB or more (master clock: 384Fs, typ.)
Logical value 109dB
•
THD + N: 0.007% or less (master clock 384Fs, typ.)
•
Rejection band attenuation: –60dB or less
80 pin LQFP (Plastic)
Applications
CD players
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
•
Supply voltage
V
DD
–0.3 to +7.0
V
•
Input voltage
V
I
–0.3 to +7.0
V
(V
SS
– 0.3V to V
DD
+ 0.3V)
•
Output voltage
V
O
–0.3 to +7.0
V
•
Storage temperature Tstg
–40 to +125 °C
•
Supply voltage difference
V
SS
– AV
SS
–0.3 to +0.3
V
V
DD
– AV
DD
–0.3 to +0.3
V
Note)
AV
DD
includes XV
DD
and AV
SS
includes XV
SS
.
Recommended Operating Conditions
•
Supply voltage
V
DD
∗
3.0 to 4.0
V
•
Operating temperature
Topr
–20 to +75
°C
∗
The V
DD
for the CXD2587Q varies according to the
playback speed.
Playback
speed
4×
2×
1×
V
DD
[V]
CD-DSP block
4.75 to 5.25
3.0 to 5.5
2.7 to 5.5
4.5 to 5.5
2.7 to 5.5
DAC block
I/O Capacitance
•
Input pin
C
I
11 (Max.)
•
Output pin
C
O
11 (Max.)
•
I/O pin
C
I/O
11 (Max.)
Note)
Measurement conditions V
DD
= V
I
= 0V
f
M
= 1MHz
pF
pF
pF
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97518-PS
CXD2587Q
Block Diagram
EMPH
WFCK
PCMD
XUGF
BCK
SYSM
C2PO
XTSL
GFS
LRCK
DAC Block
TES1
TEST
Clock
Generator
RFAC
ASYI
ASYO
BIAS
XPCK
FILO
FILI
PCO
CLTV
MDP
LOCK
SENS
DATA
XLAT
CLOK
SPOA
SPOB
XLON
SCOR
SQSO
SQCK
Signal Processor Block
Servo Block
CPU
Interface
Servo
Auto
Sequencer
Digital
CLV
Digital
PLL
Sub Code
Processor
Asymmetry
Corrector
EFM
demodurator
Error
Corrector
D/A
Interface
Serial-In
Interface
Over Sampling
Digital Filter
16K
RAM
Digital
OUT
Timing
Logic
XRST
RMUT
LMUT
XTAI
XTAO
3rd-Order
Noise Shaper
PWM
PWM
AOUT1
AIN1
LOUT1
AOUT2
AIN2
LOUT2
DOUT
SCLK
SERVO
Interface
COUT
SSTP
ATSK
MIRR
DFCT
FOK
SERVO DSP
PWM GENERATOR
FOCUS PWM
GENERATOR
TRACKING PWM
GENERATOR
SLED PWM
GENERATOR
FFDR
FRDR
TFDR
TRDR
SFDR
SRDR
MIRR
DFCT
FOK
RFDC
CE
TE
SE
FE
VC
IGEN
OPAmp
Analog SW
A/D
Converter
FOCUS SERVO
TRACKING
SERVO
SLED SERVO
ADIO
–2–
CXD2587Q
Pin Configuration
AV
DD
3
AV
DD
0
DOUT
AV
SS
3
RFAC
ASYO
AV
SS
0
FILI
ASYI
RFDC
CLTV
FILO
V
DD
V
SS
IGEN
PCO
BIAS
ADIO
CE
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
LRCK 61
PCMD 62
BCK 63
EMPH 64
XV
DD
65
XTAI 66
XTAO 67
XV
SS
68
AV
DD
1 69
AOUT1 70
AIN1 71
LOUT1 72
AV
SS
1 73
AV
SS
2 74
LOUT2 75
AIN2 76
AOUT2 77
AV
DD
2 78
RMUT 79
LMUT 80
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
40 SE
39 FE
38 VC
37 XTSL
36 TES1
35 TEST
34 V
SS
33 FRDR
32 FFDR
31 TRDR
30 TFDR
29 SRDR
28 SFDR
27 SSTP
26 MDP
25 LOCK
24 FOK
23 DFCT
22 MIRR
21 COUT
SYSM
WFCK
XUGF
XPCK
DATA
XRST
SCLK
ATSK
V
DD
SQSO
–3–
SCOR
SQCK
SENS
XLON
SPOB
CLOK
SPOA
C2PO
XLAT
GFS
TE
CXD2587Q
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Symbol
SQSO
SQCK
XRST
SYSM
DATA
XLAT
CLOK
SENS
SCLK
V
DD
ATSK
SPOA
SPOB
XLON
WFCK
XUGF
XPCK
GFS
C2PO
SCOR
COUT
MIRR
DFCT
FOK
LOCK
MDP
SSTP
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
V
SS
TEST
I/O
O
I
I
I
I
I
I
O
I
—
I/O
I
I
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
O
I
O
O
O
O
O
O
—
I
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
—
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
—
1, 0
1, 0
Output
values
1, 0
Description
Sub Q 80-bit, PCM peak and level data outputs. CD TEXT data output.
SQSO readout clock input.
System reset. Reset when low.
Mute input. Muted when high.
Serial data input from CPU.
Latch input from CPU. Serial data is latched at the falling edge.
Serial data transfer clock input from CPU.
SENS output to CPU.
SENS serial data readout clock input.
Digital power supply.
Anti-shock input/output.
Microcomputer extension interface (input A)
Microcomputer extension interface (input B)
Microcomputer extension interface (output)
WFCK output.
XUGF output. MINT1 or RFCK is output by switching with the command.
XPCK output. MNT0 is output by switching with the command.
GFS output. MNT3 or XROF is output by switching with the command.
C2PO output. GTOP is output by switching with the command.
Outputs a high signal when either subcode sync S0 or S1 is detected.
Track count signal input/output.
Mirror signal input/output.
Defect signal input/output.
Focus OK signal input/output.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS
is low eight consecutive samples, this pin outputs low. Or input when LKIN = 1.
1, Z, 0 Spindle motor servo control output.
Disc innermost track detection signal input.
Sled drive output.
Sled drive output.
Tracking drive output.
Tracking drive output.
Focus drive output.
Focus drive output.
Digital GND.
Test pin. Normally, GND.
–4–
CXD2587Q
Pin
No.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Symbol
TES1
XTSL
VC
FE
SE
TE
CE
RFDC
ADIO
AV
SS
0
IGEN
AV
DD
0
ASYO
ASYI
BIAS
RFAC
AV
SS
3
CLTV
FILO
FILI
PCO
AV
DD
3
V
SS
V
DD
DOUT
LRCK
PCMD
BCK
EMPH
XV
DD
XTAI
XTAO
XV
SS
AV
DD
1
AOUT1
AIN1
I/O
I
I
I
I
I
I
I
I
O
—
I
—
O
I
I
I
—
I
O
I
O
—
—
—
O
O
O
O
O
—
I
O
—
—
O
I
Output
values
Test pin. Normally, GND.
Description
Crystal selection input. Low when the crystal is 16.9344MHz; high when the
crystal is 33.8688MHz.
Center voltage input.
Focus error signal input.
Sled error signal input.
Tracking error signal input.
Center servo analog input.
RF signal input.
Analog Test pin. No connected.
—
Analog GND.
Operational amplifier constant current input.
—
1, 0
Analog power supply.
EFM full-swing output. (low = Vss, high = V
DD
)
Asymmetry comparator voltage input.
Asymmetry circuit constant current input.
EFM signal input.
—
Analog GND.
Multiplier VCO1 control voltage input.
Analog Master PLL filter output. (slave = digital PLL)
Master PLL filter input.
1, Z, 0
—
—
—
1, 0
1, 0
1, 0
1, 0
1, 0
—
Master PLL charge pump output.
Analog power supply.
Digital GND.
Digital power supply.
Digital Out output.
D/A interface. LR clock output f = Fs.
D/A interface. Serial data output. (two's complement, MSB first)
D/A interface. Bit clock output.
Outputs a high signal when the playback disc has emphasis, and a low
signal when there is no emphasis.
Master clock power supply.
Crystal oscillation circuit input. Master clock is externally input from this pin.
Crystal oscillation circuit output.
—
—
Master clock GND.
Analog power supply.
L ch analog output.
L ch operational amplifier input.
–5–
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