ispLSI 2192VL
2.5V In-System Programmable
SuperFAST™ High Density PLD
Features
• SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
8000 PLD Gates
96 I/O Pins, Nine Dedicated Inputs
192 Registers
High Speed Global Interconnect
Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Pinout Compatible with ispLSI 2096V and 2096VE
• 2.5V LOW VOLTAGE ARCHITECTURE
— Interfaces with Standard 3.3V Devices (Inputs and
I/Os are 3.3V Tolerant)
— 175 mA Typical Active Current
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
—
—
—
—
—
—
—
—
—
—
—
A0
Output Routing Pool
®
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Functional Block Diagram
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
Output Routing Pool
E7 E6 E5 E4 E3 E2 E1 E0
D7
D5
Output Routing Pool
D Q
A1
A2
A3
A4
A5
A6
A7
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
D6
Logic
D Q
Global Routing Pool (GRP)
Array
D Q
GLB
D4
D3
D2
D1
D0
D Q
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool
f
max
= 150 MHz Maximum Operating Frequency
t
pd
= 6.0 ns Propagation Delay
Electrically Erasable and Reprogrammable
Non-Volatile
100% Tested at Time of Manufacture
Unused Product Term Shutdown Saves Power
Description
The ispLSI 2192VL is a High Density Programmable
Logic Device containing 192 Registers, nine Dedicated
Input pins, three Dedicated Clock Input pins, two dedi-
cated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2192VL fea-
tures in-system programmability through the Boundary
Scan Test Access Port (TAP) and is 100% IEEE 1149.1
Boundary Scan Testable. The ispLSI 2192VL offers non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2192VL device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 2192VL device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
• IN-SYSTEM PROGRAMMABLE
— 2.5V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-
OR Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
—
—
—
—
—
—
Enhanced Pin Locking Capability
Three Dedicated Clock Input Pins
Synchronous and Asynchronous Clocks
Programmable Output Slew Rate Control
Flexible Pin Placement
Optimized Global Routing Pool Provides Global
Interconnectivity
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
January 2002
2192vl_04
1
CLK0
CLK1
CLK2
0139/2192VL
Specifications
ispLSI 2192VL
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Functional Block Diagram
Figure 1. ispLSI 2192VL Functional Block Diagram
I/O I/O I/O I/O
95 94 93 92
RESET
GOE 0
GOE 1
I/O I/O I/O I/O
91 90 89 88
I/O I/O I/O I/O
87 86 85 84
I/O I/O I/O I/O
83 82 81 80
IN IN
11* 10
I/O I/O I/O I/O
79 78 77 76
I/O I/O I/O I/O
75 74 73 72
I/O I/O I/O I/O
71 70 69 68
I/O I/O I/O I/O
67 66 65 64
IN
9
IN
8
Input Bus
Generic
Logic Blocks
(GLBs)
F7
F6
Output Routing Pool (ORP)
F5
F4
F3
F2
F1
F0
E7
E6
Input Bus
Output Routing Pool (ORP)
E5
E4
E3
E2
E1
E0
IN 7/TCK
IN 6/TDO
I/O 63
I/O 62
I/O 61
I/O 60
D7
I/O 0
I/O 1
I/O 2
I/O 3
A0
A1
D6
Output Routing Pool (ORP)
D5
I/O 59
I/O 58
I/O 57
Output Routing Pool (ORP)
D4
D3
D2
D1
D0
lnput Bus
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
TDI/IN 0
TMS/IN 1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
Global
Routing
Pool
(GRP)
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
CLK 0
CLK 1
Output Routing Pool (ORP)
Megablock
Input Bus
BSCAN
IN 2*
IN 3
Output Routing Pool (ORP)
Input Bus
I/O I/O I/O I/O
16 17 18 19
I/O I/O I/O I/O
20 21 22 23
I/O I/O I/O I/O
24 25 26 27
I/O I/O I/O I/O
28 29 30 31
IN4 IN 5*
I/O I/O I/O I/O
32 33 34 35
I/O I/O I/O I/O
36 37 38 39
I/O I/O I/O I/O
40 41 42 43
I/O I/O I/O I/O
44 45 46 47
Y0 Y1 Y2
*Note: Dedicated Inputs 2, 5 and 11 are not available with 128-pin packages.
2192VL Block.eps
The 2192VL contains 96 I/O cells. Each I/O cell is directly
connected to an I/O pin and can be individually pro-
grammed to be a combinatorial input, output or
bi-directional I/O pin with 3-state control, and the output
drivers can source 4mA or sink 8mA. Each output can be
programmed independently for fast or slow output slew
rate to minimize overall output switching noise. Device
pins can be safely driven to 3.3V signal levels to support
mixed-voltage systems.
Eight GLBs, 16 I/O cells, two dedicated inputs and an
ORP are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 16 universal I/O cells by the ORPs. Each ispLSI
2192VL device contains six Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2192VL device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2192VL are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration is a totem-pole
configuration. The open-drain/totem-pole option is se-
lectable through the Lattice software tools.
2
CLK 2
C0
C1
C2
C3
C4
C5
C6
C7
Specifications
ispLSI 2192VL
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Absolute Maximum Ratings
1
Supply Voltage V
cc
................................ -0.5 to +4.05V
Input Voltage Applied ............................. -0.5 to +4.05V
Off-State Output Voltage Applied .......... -0.5 to +4.05V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T
J
) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
Supply Voltage
Input Low Voltage
Input High Voltage
Commercial
Industrial
T
A
= 0°C to + 70°C
T
A
= -40°C to + 85°C
MIN.
2.3
2.3
-0.3
1.7
MAX.
2.7
2.7
0.7
3.6
UNITS
V
V
V
V
V
CC
V
IL
V
IH
Table 2-0005/2192VL
Capacitance (T
A
=25°C, f=1.0 MHz)
SYMBOL
PARAMETER
Dedicated Input Capacitance
I/O Capacitance
Clock and Global Output Enable Capacitance
TYPICAL
8
6
10
UNITS
pf
pf
pf
TEST CONDITIONS
V
CC
= 2.5V, V
IN
= 0.0V
V
CC
= 2.5V, V
I/O
= 0.0V
V
CC
= 2.5V, V
Y
= 0.0V
Table 2-0006/2192VL
C
1
C
2
C
3
Erase Reprogram Specifications
PARAMETER
Erase/Reprogram Cycles
MINIMUM
10,000
MAXIMUM
—
UNITS
Cycles
Table 2-0008/2192VL
3
Specifications
ispLSI 2192VL
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.15V from
steady-state active level.
GND to V
CC
≤
1.5ns 10% to 90%
V
CC
/2
V
CC
/2
See Figure 2
Table 2 - 0003/2192VL
Figure 2. Test Load
V
CC
R1
Device
Output
R2
CL
*
Test
Point
Output Load Conditions (see Figure 2)
TEST CONDITION
A
B
Active High
Active Low
Active High to Z
at
V
OH
-0.15V
Active Low to Z
at
V
OL
+0.15V
R1
250Ω
R2
218Ω
218Ω
CL
35pF
35pF
35pF
5pF
5pF
∞
250Ω
*
CL includes Test Fixture and Probe Capacitance.
0213A/2192VL
∞
218Ω
∞
250Ω
C
∞
Table 2-0004/2192VL
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
PARAMETER
Output Low Voltage
CONDITION
I
OL
= 100µA
I
OL
= 8mA
I
OH
= -100µA
Output High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
BSCAN
Input Pull-Up Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
I
OH
= -1mA
I
OH
= -4mA
0V
≤
V
IN
≤
V
IL
(Max.)
V
IH
(min)
≤
V
IN
≤
3.6V
0V
≤
V
IN
≤
V
IL
0V
≤
V
IN
≤
V
IL
V
CC
= 2.5V, V
OUT
= 0.5V
V
IL
= 0.0V, V
IH
= 2.5V
f
CLK
= 1 MHz
Table 2-0007/2192VL
1. One output at a time for a maximum duration of one second. V
OUT
= 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using 12 16-bit counters.
3. Typical values are at V
CC
= 2.5V and T
A
= 25°C.
4. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I
CC
.
5. With no pull-up resistors.
MIN.
—
—
V
CC
- 0.2
TYP.
—
—
—
—
—
—
—
—
—
—
175
3
MAX. UNITS
0.2
0.4
—
—
—
-10
10
-150
-150
-100
—
V
V
V
V
V
µA
µA
µA
µA
mA
mA
V
OL
V
OH
I
IL
5
I
IH
I
IL-isp
I
IL-PU
I
OS
1
I
CC
2, 4
2.0
1.8
—
—
—
—
—
—
4
Specifications
ispLSI 2192VL
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST
COND.
A
A
A
—
—
—
A
—
—
A
—
A
—
B
C
B
C
—
—
3
#
1
2
3
4
5
6
7
8
9
DESCRIPTION
1
-150
—
—
2
1
tsu2 + tco1
-135
—
—
135
95
143
5.0
—
0.0
6.0
—
0.0
—
5.5
—
—
—
—
3.5
3.5
7.5
10.0
—
—
—
—
4.5
—
—
5.5
—
8.0
—
12.0
12.0
7.0
7.0
—
—
-100
—
—
100
77
100
6.5
—
0.0
8.0
—
0.0
—
6.5
—
—
—
—
5.0
5.0
10.0
13.0
—
—
—
—
5.0
—
—
6.0
—
13.5
—
15.0
15.0
9.0
9.0
—
—
MIN. MAX. MIN. MAX. MIN. MAX.
6.0
8.5
—
—
—
—
4.0
—
—
5.0
—
6.0
—
10.0
10.0
6.0
6.0
—
—
UNITS
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
Clock Frequency with External Feedback
(
150
)
111
166
4.0
—
0.0
5.0
—
0.0
—
5.0
—
—
—
—
3.0
3.0
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay, ORP Bypass
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030C/2192VL
5
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