CXD3503R
Color Shading Correction IC for Liquid Crystal Projectors
Description
The CXD3503R is a color shading correction IC for
Sony data projectors. Used together with the Sony
LCD driver CXA2111R or CXA2112R, this IC corrects
color shading caused by the LCD panel structure or
the optical system. This IC has a built-in SRAM and
D/A converter, and 16 horizontal and 13 vertical
correction points can be set via a serial interface.
Functions
•
Generates the color shading correction signals for
the high-temperature polysilicon TFT LCD panels
used in Sony projectors
•
Supports various SVGA, XGA and SXGA signals
using 1/2 dot clock input
•
Vertical output signal interpolation using an internal
•
arithmetic circuit
Automatic determination of eliminated lines during
pulse eliminator display when used together with
the Sony timing generator ICs CXD2464R or
CXD3500R
Supports up/down and/or right/left inversion
Supports LCD panel display area switching
conversion functions
Standby and correction OFF functions
64 pin LQFP (Plastic)
Absolute Maximum Ratings
(V
SS
= 0V)
•
Supply voltage V
DD
V
SS
– 0.3 to +7.0
•
Input voltage
V
I
•
Output voltage V
O
•
Storage temperature
Tstg
•
Operating temperature
Topr
V
SS
– 0.3 to V
DD
+ 0.3
V
SS
– 0.3 to V
DD
+ 0.3
–55 to +125
–40 to +85
V
V
V
°C
°C
•
•
•
Recommended Operating Conditions
(Ta = –20 to +75°C, V
SS
= 0V)
Supply voltage V
DD
4.5 to 5.5
V
Applications
Liquid crystal projectors, etc.
Structure
Silicon gate CMOS IC
Note)
Company names and product names, etc. contained in these materials are trademarks or registered trademarks of the
respective companies.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99432-PS
CXD3503R
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Symbol
NC
NC
VST
HST
DWN
RGT
CTRL
TEST0
TEST1
TEST2
DOUT00
DOUT01
DOUT02
DOUT03
DOUT04
DOUT05
DV
SS
0
DOUT10
DOUT11
DOUT12
DOUT13
DOUT14
DOUT15
DV
DD
0
DOUT20
DOUT21
DOUT22
DOUT23
DOUT24
DOUT25
DACKO
DACKI
OLIM
DV
DD
1
I/O
—
—
I
I
I
I
I
I
I
I
O
O
O
O
O
O
—
O
O
O
O
O
O
—
O
O
O
O
O
O
O
I
I
—
Not connected
Not connected
VST pulse input
HST pulse input
Up/down inversion control input (H: down scan, L: up scan)
Right/left inversion control input (H: normal scan, L: reverse scan)
Up/down and/or right/left inversion control signal (Serial settings
selected when L.)
Test (Leave open.)
Test (Leave open.)
Test (Leave open.)
Digital data output 00
Digital data output 01
Digital data output 02
Digital data output 03
Digital data output 04
Digital data output 05
Digital GND
Digital data output 10
Digital data output 11
Digital data output 12
Digital data output 13
Digital data output 14
Digital data output 15
Digital V
DD
(5V)
Digital data output 20
Digital data output 21
Digital data output 22
Digital data output 23
Digital data output 24
Digital data output 25
DAC clock output (Connect to DACKI.)
DAC clock input (Connect to DACKO.)
Digital data output limiter (H: Hi-Z, L: digital data output)
Digital V
DD
(5V)
–3–
Description
Processing for
internal input
—
—
—
—
—
—
—
L
L
L
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CXD3503R
Pin
No.
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Symbol
DV
SS
1
DACO2
BFIN2
AOUT2
AV
SS
VRL
DACO1
BFIN1
AOUT1
VRH
AV
DD
DACO0
BFIN0
AOUT0
DV
SS
2
NC
NC
NC
NC
NC
NC
DV
DD
2
SCTR
SCLK
SDAT
HSYNC
XCLR
DV
SS
3
CKI
SLCK
I/O
—
O
I
O
—
I
O
I
O
I
—
O
I
O
—
—
—
—
—
—
—
—
I
I
I
I
I
—
I
I
Digital GND
DAC output 2
Buffer input 2
Correction signal output 2
Analog GND
Description
Processing for
internal input
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H
—
—
—
DAC output low reference voltage input
DAC output 1
Buffer input 1
Correction signal output 1
DAC output high reference voltage input
Analog power supply
DAC output 0
Buffer input 0
Correction signal output 0
Digital GND
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Digital V
DD
(5V)
Serial chip select input (serial transfer block)
Serial clock input (serial transfer block)
Serial data input (serial transfer block)
HSYNC input
Clear (L: system clear)
Digital GND
Master clock input
Clock switching (H: Internal 1/2 frequency divider used.)
–4–
CXD3503R
Electrical Characteristics
DC Characteristics
Item
Supply voltage
Input, output voltage
Input voltage 1
Symbol
V
DD
V
I
, V
O
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
Input leak current
Output leak
current
Pull-up resistor
I
IL
I
OZ
R
UP
CMOS input
CMOS input
With pull-up resistor
CMOS input
With pull-down resistor
TTL input
2.5
TTL Schmitt input
I
OH
= –4mA
I
OL
= 4mA
V
I
= V
DD
, V
SS
During high impedance
output
–10
–10
60
45
During 41MHz operation
120
90
60
V
DD
– 2.1
0.4
10
10
240
180
V
µA
µA
kΩ
kΩ
mA
0.6
V
0.7V
DD
0.3V
DD
0.7V
DD
0.3V
DD
2.2
0.8
V
V
V
Conditions
(V
DD
= 5.0 ± 0.5V, V
SS
= 0V, Topr = –40 to +85°C)
Min.
4.5
V
SS
0.7V
DD
0.3V
DD
V
Typ.
5.0
Max.
5.5
V
DD
Unit Applicable pins
V
V
∗
1
∗
4
∗
2
∗
5
∗
3
∗
6,
∗
7
∗
1,
∗
3,
∗
5
∗
7
∗
4
∗
2
Input voltage 2
Input voltage 3
Input voltage 4
Input voltage 5
Output voltage 1
Pull-down resistor
R
DN
Current consumption
I
DD
(INPUT)
∗
1
CTRL, DACKI, DWN, HST, OLIM, RGT, SLCK, VST
∗
2
TEST0, 1, 2
∗
3
HSYNC, SCLK, SCTR, SDAT
∗
4
XCLR
∗
5
CKI
(OUTPUT)
∗
6
DACKO
∗
7
DOUT00 to 05, DOUT10 to 15, DOUT20 to 25
Note)
AOUT0, 1 and 2, DACO0, 1 and 2, BFIN0, 1 and 2, VRH and VRL are not included in the DC characteristics.
–5–
京公网安备 11010802033920号
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