591BD283M000DGR datasheet, PDF

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591BD283M000DGR: DescriptionLVDS Output Clock Oscillator, 283MHz Nom,; CategoryPassive components oscillator; File Size416KB，16 Pages; ManufacturerSkyworks; Websitehttp://www.skyworksinc.com; Environmental Compliance

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591BD283M000DGR Overview

LVDS Output Clock Oscillator, 283MHz Nom,

591BD283M000DGR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	4037671556
Reach Compliance Code	compliant
YTEOL	6.65
Other features	TRI-STATE; ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT; TR
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Installation features	SURFACE MOUNT
Nominal operating frequency	283 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
Output load	100 OHM
physical size	7.0mm x 5.0mm x 1.8mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	GOLD OVER NICKEL

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S i 5 9 0 / 5 91

1 ps M

I T T E R

RYSTAL

SC ILLA TOR

(XO)

(10 M H

Z TO

810 MH

)

Features

Available with any-frequency output



frequencies from 10 to 810 MHz



3rd generation DSPLL

with superior



jitter performance: 1 ps max jitter



Better frequency stability than SAW-



based oscillators



Internal fundamental mode crystal

ensures high reliability



Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry Standard 5x7 and

3.2x5 mm packages

Pb-free/RoHS-compliant

–40 to +85 ºC operating

temperature range

Si5602

Applications



Ordering Information:

See page 8.



SONET/SDH (OC-3/12/48)



Networking



SD/HD SDI/3G SDI video

Test and measurement



Storage



FPGA/ASIC clock generation

Description

The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL

circuitry

to provide a low jitter clock at high frequencies. The Si590/591 supports any

frequency from 10 to 810 MHz. Unlike a traditional XO, where a unique

crystal is required for each output frequency, the Si590/591 uses one fixed

crystal to provide a wide range of output frequencies. This IC based

approach allows the crystal resonator to provide exceptional frequency

stability and reliability. In addition, DSPLL clock synthesis provides superior

supply noise rejection, simplifying the task of generating low jitter clocks in

noisy environments typically found in communication systems. The

Si590/591 IC based XO is factory configurable for a wide variety of user

specifications including frequency, supply voltage, output format, and

stability. Specific configurations are factory programmed at time of shipment,

thereby eliminating long lead times associated with custom oscillators.

Pin Assignments:

See page 7.

(Top View)

CLK–

GND

CLK+

Si590 (LVDS/LVPECL/CML)

Functional Block Diagram

CLK– CLK+

GND

CLK

17 k



Any-rate

10–810 MHz

DSPLL

Clock

Synthesis

Si590 (CMOS)

Fixed

Frequency

CLK–

17 k



GND

CLK+

GND

*Note: Output Enable High/Low Options Available – See Ordering Information

Si591 (LVDS/LVPECL/CML)

Rev. 1.2 6/18

Si590/591

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