CXK591000TM/YM/M
-55LL/70LL/10LL
131,072-word
×
9-bit High Speed CMOS Static RAM
Description
The CXK591000TM/YM/M is a high speed CMOS
static RAM organized as 131,072-words by 9 bits.
A polysilicon TFT cell technology realized
extremely low stand-by current and higher data
retention stability.
Special feature are low power consumption and
high speed.
The CXK591000TM/YM/M is a suitable RAM for
portable equipment with battery back up and parity
bit.
Features
•
Fast access time
CXK591000TM/YM/M
CXK591000M
32 pin SOP (PIastic)
CXK591000TM
32 pin TSOP (PIastic)
CXK591000YM
32 pin TSOP (PIastic)
(Access time)
•
•
•
•
•
-55LL
55ns (Max.)
-70LL
70ns (Max.)
-10LL
100ns (Max.)
Low standby current
CXK591000TM/YM/M
-55LL/70LL/10LL
24µA (Max.)
Low data retention current
CXK591000TM/YM/M
-55LL/70LL/10LL
14µA (Max.)
Single +5V supply: 5V ± 10%.
Low voltage date retention: 2.0V (Min.)
Broad package line-up
CXK591000TM/YM
8mm
×
20mm 32 pin TSOP Package
CXK591000M
525mil 32 pin SOP
Package
Block Diagram
A10
A11
A9
A8
A13
A15
A16
A14
A12
A7
Buffer
Row
Decoder
Memory
Matrix
1024
×
1152
V
CC
GND
A6
A5
A4
A3
A2
A1
A0
OE
WE
CE1
CE2
Buffer
I /O Gate
Column
Decoder
Function
131072 word
×
9 bit static RAM
Structure
Silicon gate CMOS IC
Buffer
I /O Buffer
I/O1 I/O9
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E93X06-PS
CXK591000TM/YM/M
Pin Configuration
(Top View)
A11
A9
A8
A13
WE
CE2
A15
Vcc
A16
A14
A12
A7
A6
A5
A4
A3
A3
A4
A5
A6
A7
A12
A14
A16
Vcc
A15
CE2
WE
A13
A8
A9
A11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
OE
31
A10
30
CE1
29
I/O9
28
I/O8
27
I/O7
Pin Description
Symbol
A16
1
A14
2
A12
3
A7
4
A6
5
A5
6
A4
7
A3
8
A2
9
A1
10
A0
11
I/O1
12
32
Vcc
31
A15
30
CE2
29
WE
28
A13
27
A8
26
A9
25
A11
24
OE
23
A10
22
CE1
21
I/O9
20
I/O8
19
I/O7
18
I/O6
17
I/O5
Description
Address input
Data input/output
Chip enable 1, 2 input
Write enable input
Output enable input
Power supply
Ground
A0 to A16
I/O1 to I/O9
CE1, CE2
WE
OE
V
CC
GND
CXK591000TM
(Standard Pinout)
26
I/O6
25
I/O5
24
GND
23
I/O4
22
I/O3
21
I/O2
20
I/O1
19
A0
18
A1
17
A2
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
A2
18
A1
19
A0
20
I/O1
21
I/O2
22
I/O3
23
I/O4
24
GND
25
I/O5
26
I/O6
27
I/O7
28
I/O8
29
I/O9
30
CE1
31
A10
32
OE
I/O2
13
I/O3
14
I/O4
15
GND
16
CXK591000YM
(Mirror Image Pinout)
CXK591000M
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Input and output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Soldering temperrature · time
Symbol
V
CC
V
IN
V
I/O
P
D
Topr
Tstg
Tsolder
(Ta = 25°C, GND = 0V)
Rating
–0.5 to +7.0
–0.5
∗
to V
CC
+ 0.5
–0.5
∗
to V
CC
+ 0.5
0.7
0 to +70
–55 to +150
235 · 10
Unit
V
V
V
W
°C
°C
°C · s
∗
V
IN
, V
I/O
= –3.0V Min. for pulse width less than 50ns.
Truth Table
CE1 CE2
H
×
L
L
L
×
L
H
H
H
OE
×
×
H
L
×
WE
×
×
H
H
L
Mode
Not selected
Not selected
Output disable
Read
Write
I/O pin
High Z
High Z
High Z
Data out
Data in
V
CC
Current
I
SB1
, I
SB2
I
SB1
, I
SB2
I
CC1
, I
CC2
, I
CC3
I
CC1
, I
CC2
, I
CC3
I
CC1
, I
CC2
, I
CC3
×:
"H" or "L"
–2–
CXK591000TM/YM/M
DC Recommended Operating Conditions
Item
Supply voltage
Input high voltage
Input low voltage
Symbol
V
CC
V
IH
V
IL
Min.
4.5
2.2
–0.3
∗
(Ta = 0 to +70°C, GND = 0V)
Typ.
5.0
—
—
Max.
5.5
V
CC
+ 0.3
0.8
Unit
V
V
V
∗
V
IL
= –3.0V Min. for pulse width less than 50ns.
Electrical Characteristics
• DC Characteristics
Item
Input leakage current
Output leakage
current
Operating power supply
current
System
I
LI
I
LO
Test conditions
V
IN
= GND to V
CC
CE1 = V
IH
or CE2 = V
IL
or
OE = V
IH
or WE = V
IL
V
I/O
= GND to V
CC
CE1 = V
IL
, CE2 = V
IH
V
IN
= V
IH
or V
IL
I
OUT
= 0mA
Min. cycle
duty = 100%
I
OUT
= 0mA
Cycle time 1µs
duty = 100%
I
OUT
= 0mA
CE1
≤
0.2V
CE2
≥
Vcc – 0.2V
V
IL
≤
0.2V
V
IH
≥
Vcc – 0.2V
CE2
≤
0.2V
CE1
≥
Vcc – 0.2V
CE2
≥
Vcc – 0.2V
CE1 = V
IH
or CE2 = V
IL
I
OH
= –1.0mA
I
OL
= 2.1mA
0 to +70°C
0 to +40°C
+25°C
-55LL
-70LL
-10LL
(V
CC
= 5V ± 10%, GND = 0V, Ta = 0 to +70°C)
Min.
–1
–1
Typ.
∗
—
—
Max.
+1
+1
Unit
µA
µA
I
CC1
—
—
—
—
8
50
45
40
17
100
80
70
mA
I
CC2
mA
Average operating current
I
CC3
—
12
24
mA
—
—
—
—
2.4
—
—
—
0.8
0.6
—
—
24
5
2.4
3
—
0.4
mA
V
V
µA
I
SB1
Standby current
I
SB2
Output high voltage
Output low voltage
∗
V
CC
= 5V, Ta = 25°C
V
OH
V
OL
–3–
CXK591000TM/YM/M
I/O capacitance
Item
Input capacitance
I/O capacitance
Symbol Test conditions
C
IN
C
I/O
V
IN
= 0V
V
I/O
= 0V
Min.
—
—
(Ta = 25°C, f = 1MHz)
Typ.
—
—
Max.
7
8
Unit
pF
pF
Note)
This parameter is sampled and is not 100% tested.
AC Characteristics
• AC test conditions
Item
Input pulse high level
Input pulse low level
Input rise time
Input fall time
(V
CC
= 5V ± 10%, Ta = 0 to +70°C)
Conditions
V
IH
= 2.2V
V
IL
= 0.8V
• Test circuit
TTL
tr = 5ns
tf = 5ns
C
L
Input and output reference level
Output load conditions
-55LL
-70LL/10LL
∗
C
L
includes scope and jig capacitances.
1.5V
C
L
∗
= 30pF, 1TTL
C
L
∗
= 100pF, 1TTL
–4–
CXK591000TM/YM/M
• Read cycle
(WE = "H")
Item
Read cycle time
Address access time
Chip enable access time (CE1)
Chip enable access time (CE2)
Symbol
t
RC
-55LL
Min.
55
—
—
—
—
15
10
5
—
—
Max.
—
55
55
55
30
—
—
—
25
25
-70LL
Min.
70
—
—
—
—
15
10
5
—
—
Max.
—
70
70
70
40
—
—
—
25
25
-10LL
Min.
100
—
—
—
—
15
10
5
—
—
Max.
—
100
100
100
50
—
—
—
35
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
AA
t
CO1
t
CO2
t
OE
Output enable to output valid
t
OH
Output hold from address change
t
LZ1
,
t
LZ2
Chip enable to output in low Z (CE1, CE2)
t
OLZ
Output enable to output in low Z (OE)
Chip disable to output in high Z (CE1, CE2)
t
HZ1
,
t
HZ2
∗
t
OHZ
∗
Output disable to output in high Z (OE)
referred to as output voltage levels.
∗
t
HZ1
, t
HZ2
and t
OHZ
are defined as the time required for outputs to turn to high impedance state and are not
• Write cycle
Item
Write cycle time
Address valid to end of write
Chip enable to end of write
Data to write time overlap
Data hold from write time
Write pulse width
Address setup time
Write recovery time (WE)
Write recovery time (CE1, CE2)
Output active from end of write
Write to output in high Z
Symbol
-55LL
Min.
Max.
—
—
—
—
—
—
—
—
—
—
25
-70LL
Min.
70
60
60
30
0
50
0
0
0
10
—
Max.
—
—
—
—
—
—
—
—
—
—
25
-10LL
Min.
100
70
70
40
0
60
0
0
0
10
—
Max.
—
—
—
—
—
—
—
—
—
—
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
WC
t
AW
t
CW
t
DW
t
DH
t
WP
t
AS
t
WR
t
WR1
t
OW
t
WHZ
∗
55
50
50
25
0
40
0
0
0
10
—
∗
t
WHZ
is defined as the time required for outputs to turn to high impedance state and is not referred to as
output voltage level.
–5–
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