IDT72811L25TFI8 datasheet, PDF

Datasheet> All Categories > storage> storage> IDT72811L25TFI8

IDT72811L25TFI8: DescriptionFIFO, 512X9, 15ns, Synchronous, CMOS, PQFP64, SLIM, TQFP-64; Categorystorage storage; File Size154KB，16 Pages; ManufacturerIDT (Integrated Device Technology)

Download Datasheet Parametric View All

IDT72811L25TFI8 Overview

FIFO, 512X9, 15ns, Synchronous, CMOS, PQFP64, SLIM, TQFP-64

IDT72811L25TFI8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	SLIM, TQFP-64
Contacts	64
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	15 ns
Maximum clock frequency (fCLK)	40 MHz
period time	25 ns
JESD-30 code	S-PQFP-G64
JESD-609 code	e0
length	10 mm
memory density	4608 bit
Memory IC Type	OTHER FIFO
memory width	9
Humidity sensitivity level	3
Number of functions	2
Number of terminals	64
word count	512 words
character code	512
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512X9
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP64,.47SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	5 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.01 A
Maximum slew rate	0.06 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	10 mm
Base Number Matches	1

Preview

Download Datasheet

View All

DUAL CMOS SyncFIFO™

DUAL 256 x 9, DUAL 512 x 9,

DUAL 1,024 x 9, DUAL 2,048 x 9,

DUAL 4,096 x 9, DUAL 8,192 x 9

IDT72801

IDT72811

IDT72821

IDT72831

IDT72841

IDT72851

.EATURES:

•

The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs

The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs

The IDT72821 is equivalent to two IDT72221 1,024 x 9 FIFOs

The IDT72831 is equivalent to two IDT72231 2,048 x 9 FIFOs

The IDT72841 is equivalent to two IDT72241 4,096 x 9 FIFOs

The IDT72851 is equivalent to two IDT72251 8,192 x 9 FIFOs

Offers optimal combination of large capacity, high speed,

design flexibility and small footprint

Ideal for prioritization, bidirectional, and width expansion

applications

10 ns read/write cycle time for the IDT72801/72811/72821/72831/

72841 (excluding the IDT72851)

15 ns read/write cycle time for the IDT72851

Separate control lines and data lines for each FIFO

Separate Empty, Full, Programmable Almost-Empty and Almost-

Full flags for each FIFO

Enable puts output data lines in high-impedance state

Space-saving 64-pin Thin Quad Flat Pack (TQFP) and Slim Thin

Quad Flatpack (STQFP)

Industrial temperature range (–40°C to +85°C) is available

DESCRIPTION:

The IDT72801/72811/72821/72831/72841/72851 are dual synchronous

(clocked) FIFOs. The device is functionally equivalent to two IDT72201/72211/

72221/72231/72241/72251 FIFOs in a single package with all associated

control, data, and flag lines assigned to separate pins.

Each of the two FIFOs (designated FIFO A and FIFO B) contained in the

IDT72801/72811/72821/72831/72841/72851 has a 9-bit input data port (DA0

- DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8, QB0 - QB8). Each

input port is controlled by a free-running clock (WCLKA, WCLKB), and two Write

Enable pins (WENA1, WENA2,

WENB1,

WENB2). Data is written into each of

the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB)

when the appropriate write enable pins are asserted.

The output port of each FIFO bank is controlled by its associated clock pin

(RCLKA, RCLKB) and two Read Enable pins (RENA1,

RENA2, RENB1,

RENB2).

The Read Clock can be tied to the Write Clock for single clock operation

or the two clocks can run asynchronous of one another for dual clock operation.

An Output Enable pin (OEA,

OEB)

is provided on the read port of each FIFO

for three-state output control.

Each of the two FIFOs has two fixed flags, Empty (EFA,

EFB)

and Full (FFA,

FFB).

Two programmable flags, Almost-Empty (PAEA,

PAEB)

and Almost-Full

(PAFA,

PAFB),

are provided for each FIFO bank to improve memory utilization.

If not programmed, the programmable flags default to empty+7 for

PAEA

and

PAEB,

and full-7 for

PAFA

and

PAFB.

The IDT72801/72811/72821/72831/72841/72851 architecture lends itself

to many flexible configurations such as:

• 2-level priority data buffering

• Bidirectional operation

• Width expansion

• Depth expansion

These FIFOs is fabricated using IDT's high-performance submicron

CMOS technology.

.UNCTIONAL BLOCK DIAGRAM

WCLKA

WENA1

WENA2

DA0 - DA8

EFA

PAEA

PAFA

LDA

FFA

WCLKB

WENB1

WENB2

DB0 - DB8

LDB

INPUT REGISTER

OFFSET REGISTER

FLAG

LOGIC

INPUT REGISTER

OFFSET REGISTER

EFB

PAEB

PAFB

FFB

WRITE CONTROL

LOGIC

RAM ARRAY

256 x 9, 512 x 9,

1024 x 9, 2048 x 9,

4096 x 9, 8192 x 9

WRITE CONTROL

LOGIC

RAM ARRAY

256 x 9, 512 x 9,

1024 x 9, 2048 x 9,

4096 x 9, 8192 x 9

FLAG

LOGIC

WRITE POINTER

READ POINTER

WRITE POINTER

READ POINTER

READ CONTROL

LOGIC

READ CONTROL

LOGIC

OUTPUT REGISTER

RESET LOGIC

OUTPUT REGISTER

RSA

OEA

QA0 - QA8

RCLKA

RENA1

RENA2

RSB

OEB

QB0 - QB8

RCLKB

RENB1

RENB2

3034 drw 01

SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE



2001

Integrated Device Technology, Inc.

APRIL 2001

DSC-3034/1

Recommended Resources

Simple 100W inverter circuit diagram design

Energy saving neon light converter circuit

555 respiratory monitor circuit

High input voltage integrated regulated power supply circuit composed of CW200 Part 2

Changhong N2918 power supply

Radar energy-saving lamp holder circuit schematic diagram

TMS320C6455 GPIO interruption problem: I am new to DSP and I have a problem. Please help me! ! When configuring GPIO5 as a hardware interrupt, I use the code in CSL to configure it. The pin selected is CSL_GPIO_PIN5. In the datasheet, the ...; Joying DSP and ARM Processors

How to select TVS: This is MicroNotes ,which writed by Kent Walters .Tell you how to select TVS....; 安_然 Analog electronics

[Zero-knowledge ESP8266 tutorial] Quick Start 8-Reading analog values: After we made a buzzer together last time, your brain circuits were very fast. Now let's strike while the iron is hot and think about it. In the past, we have been using digital pins (such as D0, D1, ...; roc2 stm32/stm8

2808 Minimum System: Is there any expert here who has made a minimal system for 2808?...; 安_然 Microcontroller MCU

Help: Power supply design for a single LED: I have an LED that needs to be driven, 6.5V, 20mA. I need to make a driver that can control the current. I don't need to adjust it continuously, I just need to switch between 0mA and 20mA. What is the...; aiwenzx LED Zone

About Protell99's Prospects: At this stage, many friends, especially those who have just graduated from school, like to use Protell99. I feel that this software is really good, but many of my friends are not optimistic about it a...; longbin518.love PCB Design

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components