BU-63925F2-391L datasheet, PDF

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BU-63925F2-391L: DescriptionMil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CDFP70, 1.90 X 1 INCH, 0.215 INCH HEIGHT, CERAMIC, FP-70; CategoryThe embedded processor and controller Microcontrollers and processors; File Size987KB，48 Pages; ManufacturerData Device Corporation

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BU-63925F2-391L Overview

Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CDFP70, 1.90 X 1 INCH, 0.215 INCH HEIGHT, CERAMIC, FP-70

BU-63925F2-391L Parametric

Parameter Name	Attribute value
Objectid	1334450626
package instruction	DFP,
Reach Compliance Code	compliant
Country Of Origin	Taiwan, USA
YTEOL	7.5
Other features	LG-MAX; WD-MAX
Address bus width	16
boundary scan	NO
maximum clock frequency	16 MHz
letter of agreement	MIL-STD-1553A; MIL-STD-1553B; MCAIR; STANAG-3838
Data encoding/decoding methods	BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	0.125 MBps
External data bus width	16
JESD-30 code	R-CDFP-F70
JESD-609 code	e0
length	48.26 mm
low power mode	YES
Number of serial I/Os	2
Number of terminals	70
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Package shape	RECTANGULAR
Package form	FLATPACK
Maximum seat height	5.46 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
width	25.4 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553

BU-63925F2-391L Preview

BU-63825

SPACE LEVEL MIL-STD-1553

BC/RT/MT

ADVANCED COMMUNICATION ENGINE

(SP’ACE II) TERMINAL

FEATURES

Make sure the next

Card you purchase

has...

•

Direct Replacement for BU-61582

and BU-61583

•

Radiation Tolerant & Radiation

Hardened Versions

•

Fully Integrated 1553 Terminal

•

Flexible Processor Interface

•

16K x 16 Internal RAM

•

Automatic BC Retries

•

Programmable BC Gap Times

•

BC Frame Auto-Repeat

•

Intelligent RT Data Buffering

•

Ceramic Package

DESCRIPTION

The BU-63825(925) is a fully hardware & software compatible, direct

drop-in replacement for the BU-61582(83).

DDC’s BU-63825(925) Space Advanced Communication Engine

(Sp’ACE II) is a radiation hardened version of the BU-61580(81) ACE

terminal. DDC supplies the BU-63825 with enhanced screening for

space and other high reliability applications.

The BU-63825 provides a complete integrated BC/RT/MT interface

between a host processor and a MIL-STD-1553 bus. The

BU-63825(925) provides functional and software compatibility with

the standard BU-61580(81) product and is packaged in the same 1.9

square-inch package footprint.

As an option, DDC can supply the BU-63825 with space level screen-

ing. This entails enhancements in the areas of element evaluation

and screening procedures for active and passive elements, as well as

the manufacturing and screening processes used in producing the

terminals.

The BU-63825 integrates dual transceiver, protocol, memory man-

agement and processor interface logic, and 16K words of RAM in the

choice of 70-pin DIP or flat pack packages. Transceiverless versions

may be used with an external electrical or fiber optic transceiver.

To minimize board space and ‘glue’ logic, the Sp’ACE II terminals

provide flexibility in interfacing to a host processor and internal/exter-

nal RAM.

•

Multiple Ordering Options;

+5V (Only)

+5V/-15V

+5V/-12V

+5V/Transceiverless

+5V (Only, with Transmit Inhibits)

WARNING: EXPORT CONTROLLED PRODUCT

This data sheet or product brief consists of Data De-

vice Corporation general product information that does

not contain controlled technical data as defined in the

International in Arms Regulations (ITAR) Part 120.10 or

Export Administration Regulations (EAR) Part 734.7-11.

The technology described herein is controlled under the

EAR and may not be exported without proper authoriza-

tion by the U.S. Department of Commerce as determined

on a case by case basis.

FOR MORE INFORMATION CONTACT:

Data Device Corporation

105 Wilbur Place

Bohemia, New York 11716

631-567-5600 Fax: 631-567-7358

www.ddc-web.com

Technical Support:

1-800-DDC-5757 ext. 7677 or 7381

7771

All trademarks are the property of their respective owners.

Data Device Corporation

www.ddc-web.com

16K X 16

SHARED

RAM

TRANSCEIVER

DATA BUS

DUAL

ENCODER/DECODER,

MULTIPROTOCOL

AND

MEMORY

MANAGEMENT

ADDRESS BUS

ADDRESS

BUFFERS

DATA

BUFFERS

D15-D0

PROCESSOR

DATA BUS

A15-A0

PROCESSOR

ADDRESS BUS

TRANSCEIVER

TRANSPARENT/BUFFERED, STRBD, SELECT,

RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,

MSB/LSB/DTGRT

IOEN, MEMENA-OUT, READYD

ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,

8/16-BIT/DTREQ, POLARITY_SEL/DTACK

INT

PROCESSOR

AND

MEMORY

CONTROL

INTERRUPT

REQUEST

PROCESSOR

AND

MEMORY

INTERFACE

LOGIC

CH. A

CH. B

RT ADDRESS

RTAD4-RTAD0, RTADP

INCMD

MISCELLANEOUS

CLK_IN, TAG_CLK,

MSTCLR,SSFLAG/EXT_TRG

DS-BU-63825-T

1/17

FIGURE 1. BU-63825 BLOCK DIAGRAM

TABLE 1. SP’ACE II SERIES SPECIFICATIONS

PARAMETER

ABSOLUTE MAXIMUM RATING

Supply Voltage



Logic +5V



Transceiver +5V



-15V



-12V

Logic



Voltage Input Range

RECEIVER

Differential Input Resistance

X1/X2 (Notes 1-6)

X3/X6 (Notes 1-6)

Differential Input Capacitance

X1/X2 (Notes 1-6)

X3/X6 (Notes 1-6)

Threshold Voltage, Transformer

Coupled, Measured on Stub

Common Mode Voltage (Note 7)

TRANSMITTER

Differential Output Voltage



Direct Coupled Across 35

Ω,

Measured on Bus



Transformer Coupled Across

Ω,

Measured on Bus

Output Noise, Differential (Direct

Coupled)

Output Offset Voltage, Transformer

Coupled Across 70 ohms

Rise/Fall Time

LOGIC (Note 12)

= 5.5V)

MSTCLR, CLOCK_IN, STRBD

All other inputs

= 4.5V)

MSTCLR, CLOCK_IN, STRBD

All other inputs

Hysteresis

MSTCLR, CLOCK_IN, STRBD

=5.5V, V

=2.7V)

CLOCK_IN

All other inputs

=5.5V, V

=0.0V)

CLOCK_IN

All other inputs

=4.5V, I

=max)

=(V

=4.5V, I

=max)

=4.5V)(Note 13)

= (V

=4.5V)

POWER SUPPLY REQUIREMENTS

Voltages/Tolerances



BU-63825/925X0

• +5V (Logic)



BU-63825/925X1

• +5V (Logic)

• +5V ( Ch. A, Ch. B)

• V



BU-63825/925X2

• +5V (Logic)

• +5V ( Ch. A, Ch. B)

• V

MIN

TYP

MAX

UNITS

TABLE 1. SP’ACE II SERIES SPECIFICATIONS

(CONT)

PARAMETER

MIN

TYP

MAX

UNITS

POWER SUPPLY REQUIREMENTS

(Cont’d)

Voltages/Tolerances (cont’d)



BU-63825/925X3/X6 (+5V Only)

• +5V (Logic)

• +5V ( Ch. A, Ch. B)

Current Drain (Total Hybrid)



BU-63825/925X0

• +5V (Logic)



BU-63825/925X1

• +5V (Note 10)

• -15V Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle



BU-63825/925X2

• +5V (Note 10)

• -12V Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle



BU-63825/925X3/X6

(+5V) (Logic, CH. A & CH. B)

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

POWER DISSIPATION

Total Hybrid



BU-63825/925X0



BU-63825/925X1

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle



BU-63825/925X2

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle



BU-63825/925X3/X6

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

Hottest Die



BU-63825/925X0



BU-63825/925X1

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle



BU-63825/925X2

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle



BU-63825/925X3/X6

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

-0.5

+0.5

-0.5

6.5

7.0

-18.0

+0.5

4.5

4.75

5.0

140

105

180

140

130

230

5.5

5.25

190

240

108

175

270

240

120

185

305

250

355

460

670

2.5

0.860

kΩ

Vp-p

Vpeak

Vp-p

mVp-p,

diff

nsec

-250

100

150

250

300

0.250

0.875

1.22

1.475

2.0

0.86

1.16

1.46

2.06

0.750

2.1

2.5

2.97

3.77

1.92

2.35

2.84

3.71

1.34

1.57

1.79

2.23

3.85

1.35

0.8

0.5

-10

-400

-10

-600

+10

-20

+10

-60

0.5

-8

µA

0.225

0.335

0.600

0.860

1.385

0.290

0.590

0.890

1.490

0.50

0.68

1.06

1.45

2.23

0.59

0.92

1.36

2.16

0.28

0.51

0.75

1.22

4.5

5.0

5.5

-15.75

5.5

-12.6

4.5

5.0

4.5

5.0

-14.25 -15.0

4.5

-11.4

5.0

-12.0

Data Device Corporation

www.ddc-web.com

DS-BU-63825-T

1/17

TABLE 1. SP’ACE II SERIES SPECS (CONT)

PARAMETER

CLOCK INPUT

Frequency



Nominal Value (programmable)

• Default Mode

• Option



Long Term Tolerance

• 1553A Compliance

• 1553B Compliance



Short Term Tolerance,1 second

• 1553A Compliance

• 1553B Compliance



Duty Cycle

1553 MESSAGE TIMING

Completion of CPU Write (BC Start-

to-Start of Next Message)

BC Intermessage Gap (Note 8)

BC/RT/MT Response Timeout (Note



18.5 nominal



22.5 nominal



50.5 nominal



128.0 nominal

Transmitter Watchdog Timeout

RT Response Time (Note 11)

THERMAL

Thermal Resistance, Junction-to-

Case,

Hottest Die (θ

)



BU-63825/925X0



BU-63825/925X1



BU-63825/925X2



BU-63825/925X3/X6

Operating Junction Temperature

Storage Temperature

Lead Temperature

(soldering, 10 sec.)

PHYSICAL CHARACTERISTICS

Size



70-pin DIP, Flat Pack, Gull Lead

Weight



70-pin DIP, Flat Pack, Gull Lead

MIN

TYP

MAX

UNITS

16.0

12.0

-0.01

-0.10

-.001

-0.01

MHz

0.01

0.10

0.001

0.01

µs

19.5

23.5

51.5

131

µs

TABLE 1 NOTES (cont)

(9) Software programmable (4 options). Includes RT-to-RT Timeout

(Mid-Parity of Transmit Command to Mid-Sync of Transmitting RT

Status).

(10) For both +5 V logic and transceiver. +5 V for channels A and B.

(11) Measured from mid-parity crossing of Command Word to mid-sync

crossing of RT's Status Word.

(12) MSTCLR, CLOCK_IN, and STRBD are CMOS inputs with hystere-

sis. Remainder are TTL.

(13) Minus sign indicates direction of current flow.

2.5

9.5

17.5

21.5

49.5

128

18.5

22.5

50.5

129.5

668

INTRODUCTION

DDC’s Sp’ACE II series of integrated BC/RT/MT hybrids provide

a complete, flexible interface between a microprocessor and a

MIL-STD-1553A, B Notice 2, McAir, or STANAG 3838 bus,

implementing Bus Controller, Remote Terminal (RT) and Monitor

Terminal (MT) modes. Packaged in a single 1.9 square inch

70-pin DIP, surface mountable Flat Pack or Gull Lead, the

Sp’ACE II series contains dual low-power transceivers and

encoder/decoders, complete BC/RT/MT multiprotocol logic,

memory management and interrupt logic, 16K X 16 of shared

static RAM and a direct, buffered interface to a host processor

bus.

The BU-63825 contains internal address latches and bidirec-

tional data buffers to provide a direct interface to a host proces-

sor bus. The BU-63825 may be interfaced directly to both 16-bit

and 8-bit microprocessors (Please see Appendix G in the ACE

User’s Guide for Product Advisory regarding SP’ACE and

SP’ACE II operating in 8-bit Buffered Non-Zero Wait Mode) in a

buffered shared RAM configuration. In addition, the Sp’ACE II

may connect to a 16-bit processor bus via a Direct Memory

Access (DMA) interface. The BU-63825 includes 16K words of

buffered RAM. Alternatively, the Sp’ACE II may be interfaced to

as much as 64k words of external RAM in either the shared RAM

or DMA configurations.

The Sp’ACE II RT mode is multiprotocol, supporting MIL-STD-

1553A, MIL-STD-1553B Notice 2, and STANAG 3838 (including

EFAbus).

The memory management scheme for RT mode provides an

option for separation of broadcast data, in compliance with

1553B Notice 2. Both double buffer and circular buffer options

are programmable by subaddress. These features serve to

ensure data consistency and to off-load the host processor for

bulk data transfer applications.

The Sp’ACE II series implements three monitor modes: a word

monitor, a selective message monitor, and a combined RT/selec-

tive monitor.

Other features include options for automatic retries and program-

mable intermessage gap for BC mode, an internal Time Tag

7.10

7.82

-55

-65

150

+300

°C/W

°C

1.9 X 1.0 X 0.215

(48.26 x 25.4 x 5.46)

0.6

(17)

in.

(mm)

(g)

TABLE 1 NOTES: Notes 1 through 6 are applicable to the Receiver

Differential Resistance and Differential Capacitance specifications:

(1) Specifications include both transmitter and receiver (tied together

internally).

(2) Measurement of impedance is directly between pins TX/RX A(B)

and TX/RX A(B) of the Sp’ACE II Series hybrid.

(3) Assuming the connection of all power and ground inputs to the

hybrid.

(4) The specifications are applicable for both unpowered and powered

conditions.

(5) The specifications assume a 2 volt rms balanced, differential, sinu-

soidal input. The applicable frequency range is 75 kHz to 1 MHz.

(6) Minimum resistance and maximum capacitance parameters are

guaranteed, but not tested, over the operating range.

(7) Assumes a common mode voltage within the frequency range of dc

to 2 MHz, applied to pins of the isolation transformer on the stub

side (either direct or transformer coupled), referenced to hybrid

ground. Use a DDC recommended transformer or other transformer

that provides an equivalent minimum CMRR.

(8) Typical value for minimum intermessage gap time. Under software

control, may be lengthened to (65,535 µs minus message time), in

increments of 1 µs.

Data Device Corporation

www.ddc-web.com

DS-BU-63825-T

1/17

illegalization for RT mode.

FUNCTIONAL OVERVIEW

TRANSCEIVERS

For the +5 V and -15 V/-12 V front end, the BU-63825X1(X2)

uses low-power bipolar analog monolithic and thin-film hybrid

technology. The transceiver requires +5 V and -15 V (-12 V) only

(requiring no +15 V/+12 V) and includes voltage source transmit-

ters. The BU-63825X3(X6) utilizes low-power BiCMOS analog

monolithic and thin film hybrid technology as well but requires

+5V only. The voltage source transmitters provide superior line

driving capability for long cables and heavy amounts of bus load-

ing.

The receiver sections of the BU-63825 are fully compliant

with MIL-STD-1553B in terms of front end overvoltage pro-

tection, threshold, common mode rejection, and word error

rate. In addition, the receiver filters have been designed for

optimal operation with the M-Rad chip’s Manchester II decod-

ers.

M-RAD DIGITAL MONOLITHIC

The M-Rad digital monolithic represents the cornerstone ele-

ment of the BU-63825 Sp’ACE II family of terminals. The M-Rad

chip is actually a radiation hardened version of DDC’s M’

(M-prime) monolithic which is the key building block behind

DDC’s non-radiation hardened BU-61580 ACE series of termi-

nals. As such, the M-Rad possesses all the enhanced hardware

and software features which have made the BU-61580 ACE the

industry standard 1553 interface component.

The M-Rad chip consists of a dual encoder/decoder; complete

protocol for Bus Controller (BC), 1553A/B/McAir Remote Terminal

(RT), and Monitor (MT) modes; memory management and inter-

rupt logic; a flexible, buffered interface to a host processor bus

and optional external RAM. Reference the region within the dot-

ted line of FIGURE 1. Besides realizing all the protocol, memory

management, and interface functions of the earlier AIM-HY

series, the M-Rad chip includes a large number of enhance-

ments to facilitate hardware and software design, and to further

off-load the 1553 terminal’s host processor.

DECODERS

The default mode of operation for the BU-63825 BC/RT/MT

requires a 16 MHz clock input. If needed, a software program-

mable option allows the device to be operated from a 12 MHz

clock input. Most current 1553 decoders sample using a 10 MHz

or 12 MHz clock. In the 16 MHz mode (or 12 MHz), the decoders

sample using both clock edges; this provides a sampling rate of

32 MHz or 24 MHz. The faster sampling rate for the M-Rad’s

Manchester II decoders provides superior performance in terms

of bit error rate and zero-crossing distortion tolerance.

For interfacing to fiber optic transceivers for MIL-STD-1773

applications, a transceiverless version of the Sp’ACE II can be

used. These versions provide a register programmable option for

a direct interface to the single-ended outputs of a fiber optic

receiver. No external logic is needed.

TIME TAGGING

The Sp’ACE II includes an internal read/writable Time Tag

a programmable resolution of either 2, 4, 8, 16, 32, or 64 µs per

LSB. Also, the Time Tag Register may be clocked from an exter-

nal oscillator. Another option allows software controlled incre-

menting of the Time Tag Register. This supports self-test for the

Time Tag Register. For each message processed, the value of

the Time Tag register is loaded into the second location of the

respective descriptor stack entry (“TIME TAG WORD”) for both

BC and RT modes.

Additional provided options will: clear the Time Tag Register fol-

lowing a Synchronize (without data) mode command or load the

Time Tag Register following a Synchronize (with data) mode

command; enable an interrupt request and a bit setting in the

Interrupt Status Register when the Time Tag Register rolls over

from FFFF to 0000. Assuming the Time Tag Register is not

loaded or reset, this will occur at approximately 4 second time

intervals, for 64 µs/LSB resolution, down to 131 ms intervals,

for 2 µs/LSB resolution.

Another programmable option for RT mode is the automatic clear-

ing of the Service Request Status Word bit following the

BU-63825’s response to a Transmit Vector Word mode command.

INTERRUPTS

The Sp’ACE II series components provide many programmable

options for interrupt generation and handling. The interrupt out-

put pin INT has three software programmable modes of opera-

tion: a pulse, a level output cleared under software control, or a

level output automatically cleared following a read of the Interrupt

Status Register. Individual interrupts are enabled by the Interrupt

Mask Register. The host processor may easily determine the

cause of the interrupt by using the Interrupt Status Register. The

Interrupt Status Register provides the current state of the inter-

rupt conditions. The Interrupt Status Register may be updated in

two ways. In the standard interrupt handling mode, a particular

bit in the Interrupt Status Register will be updated only if the

condition exists and the corresponding bit in the Interrupt Mask

particular bit in the Interrupt Status Register will be updated if

the condition exists regardless of the contents of the corre-

sponding Interrupt Mask Register bit. In any case, the respective

Interrupt Mask Register bit enables an interrupt for a particular

condition.

Data Device Corporation

www.ddc-web.com

DS-BU-63825-T

1/17

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