M2060/M2061 Series
SPECIFICATION FOR 3.2x5.0mm LVPECL/LVDS SMT OSCILLATOR
FEATURES
LVPECL/LVDS Differential Output
RMS Phase Jitter < 100 fs, 12 kHz to 20 MHz
(156.25 MHz, PECL output)
Low Phase Noise
rd
3 Overtone crystal technology
Compliant to RoHS directive
APPLICATIONS
10 Gigabit Ethernet switches/routers
Network Interface
Ordering Information:
Product Family
(Supply Voltage Option)
Temperature Range
Code
2
6
Value
-40 °C to +85 °C
-20 °C to +70 °C
Stability *
Code
3
4
6
8
Value
±100 ppm
±50 ppm
±25 ppm
±20 ppm
Code
B
U
G
Enable/Disable
Value
Enable High (pad 1)
No Enable/Disable
Enable High (pad 2)
Logic Type
Code
P
L
Value
LVPECL
LVDS
Package/Lead
Configuration
Code
N
Value
Leadless
Frequency
M2060
(3.3V)
XXX.XXXX MHz
M2061
(2.5V)
Example: M206024BPN 156.2500 MHz
M2060
2
4
B
P
Stability includes initial tolerance @ +25°C, deviation over operating temperature, variations to supply voltage, load, vibration and shock
.
N
156.2500 MHz
LVPECL Electrical Specifications:
Parameter
Frequency of Operation
Frequency Stability
Aging
Output Type
Output Load
Symmetry (duty cycle)
Logic Level “1”
Logic Level “0”
Rise/Fall Time
Start-up Time
Enable Logic
Disable Logic
Operating Voltage
Supply Current
Phase Jitter (RMS)
V
CC
I
CC
Φ
J
3.135
3.300
Other Parameters
0.100
ps
12 KHz to 20 MHz
156.25 MHz
05/02/17
Symbol
F
O
F/F
Min.
25
Typ.
Max.
220
Units
MHz
Conditions
Frequency Stability
-5
See ordering information
+5
ppm
1 year
st
RF Output
LVPECL Compatible
50 Ω to (Vcc-2.0) VDC
V
OH
V
OH
T
DC
T
R
/T
F
T
SU
45
V
cc
-1.025
V
cc
-1.810
70% V
CC
or
N/C
30% V
CC
55
V
cc
-0.880
V
cc
-1.620
0.4
10
V
%
V
V
ns
ms
V
V
V
mA
Ref. to 50% of waveform
20% to 80% of waveform
T
ambient
= +25°C
Pad 1 or Pad 2:
Output Enabled
Pad 1 or Pad 2:
Output Disabled to high-Z
0.2
Supply Voltage & Power Consumption
3.465
75
Page 1 of 6
M2060/M2061 Series
SPECIFICATION FOR 3.2x5.0mm LVPECL/LVDS SMT OSCILLATOR
LVDS Electrical Specifications:
Parameter
Frequency of Operation
Frequency Stability
Aging
Output Type
Output Load
Symmetry (duty cycle)
Differential Output
Voltage
Output Offset Voltage
Rise/Fall Time
Start-up Time
Enable Logic
Disable Logic
Operating Voltage
Supply Current
Phase Jitter (RMS)
V
CC
I
CC
Φ
J
3.135
3.300
Other Parameters
0.150
ps
12 KHz to 20 MHz
156.25 MHz
Symbol
F
O
F/F
-5
Min.
25
Typ.
Max.
220
Units
MHz
Conditions
Frequency Stability
See ordering information
+5
ppm
1 year
st
RF Output
LVDS Compatible
100 Ω Differential
V
OH
V
DIFF
V
OS
T
R
/T
F
T
SU
45
250
1.125
70% V
CC
or
N/C
30% V
CC
350
1.250
0.2
55
450
1.375
0.4
10
V
%
mV
V
ns
ms
V
V
V
mA
Ref. to 50% of waveform
peak-to-peak differential
output voltage
20% to 80% of waveform
T
ambient
= +25°C
Pad 1 or Pad 2:
Output Enabled
Pad 1 or Pad 2:
Output Disabled to high-Z
Supply Voltage & Power Consumption
3.465
40
Environmental & Packaging Requirements:
Storage Temperature
Mechanical Shock
Vibration
Aging
Humidity
Thermal Cycle
Hermeticity
Moisture Sensitivity Level
Solderability
Max. Soldering Conditions
Pad Termination
Package Type
-55°C to 125°C
Per MIL-STD-202, Method 213, Condition E
Per MIL-STD-202, Method 204D, Condition D
+85°C ±3°C, 720H (No BIAS)
+40°C ±2°CX90~95%, 96H (NO BIAS)
Per MIL-STD-883, Method 1011, Condition A
-8
Per MIL-STD-202, Method 112 (1 x 10 atm cc/s of Helium)
MSL1
Per EIAJ-STD-002, Method 208
See solder profile, Figure 1
Gold, 1 µm maximum thickness
6-pad 3.2 X 5.0 mm leadless ceramic. RoHS compliant.
Page 2 of 6
M2060/M2061 Series
SPECIFICATION FOR 3.2x5.0mm LVPECL/LVDS SMT OSCILLATOR
Typical LVPECL Test Circuit & Load Circuit Diagrams:
Typical LVDS Test Circuit & Load Circuit Diagrams:
Page 4 of 6
Embedded System
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