SONY
®
CXK77P36E160GB / CXK77P18E160GB
4/42/43/44
Preliminary
16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)
8Mb LW R-L w/ EC HSTL High Speed Synchronous SRAMs (256K x 36 or 512K x 18)
Description
The CXK77P36E160GB (organized as 524,288 words by 36 bits) and the CXK77P18E160GB (organized as 1,048,576 words
by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input
registers, high speed RAM, output latches, and a one-deep write buffer onto a single monolithic IC. Register - Latch (R-L) read
operations and Late Write (LW) write operations are supported, providing a high-performance user interface.
Two distinct R-L modes of operation are supported, selectable via the M2 mode pin. When M2 is “high”, these devices function
as conventional 16Mb R-L SRAMs, and pin 2B functions as a conventional SA address input. When M2 is “low”, these devices
function as Error-Correcting (EC) 8Mb R-L SRAMs, and pin 2B is ignored.
When Error-Correcting 8Mb R-L mode is selected, the SRAM is divided into two banks internally - a “primary” bank and a
“secondary” bank. During write operations, input data is ultimately written to both banks internally (through one stage of write
pipelining). During read operations, data is read from both banks internally, and each byte of primary bank data is individually
parity-checked. If the parity of a particular byte of primary data is correct (that is, “odd”), it is driven valid externally. If the
parity of a particular byte of primary data is incorrect (that is, “even”), it is discarded, and the corresponding byte of secondary
bank data is driven valid externally. Primary / secondary bank data selection is performed on each data byte independently.
Data read from the secondary bank is NOT parity-checked.
Data read from the write buffer is NOT parity-checked.
All address and control input signals except ZZ (Sleep Mode) are registered on the rising edge of K (Input Clock).
During read operations, output data is driven valid from the falling edge of K, one half clock cycle after the address is registered.
During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.
The output drivers are series terminated, and the output impedance is programmable through an external impedance matching
resistor RQ. By connecting RQ between ZQ and V
SS
, the output impedance of all DQ pins can be precisely controlled.
Sleep (power down) mode control is provided through the asynchronous ZZ input. 250 MHz operation is obtained from a single
3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.
Features
•
4 Speed Bins
-4 (-4A) (-4B)
-42 (-42A) (-42B)
-43 (-43A) (-43B)
-44
Cycle Time / Access Time
4.0ns / 3.9ns (3.8ns) (3.7ns)
4.2ns / 4.2ns (4.1ns) (4.0ns)
4.3ns / 4.5ns (4.4ns) (4.3ns)
4.4ns / 4.7ns
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single 3.3V power supply (V
DD
): 3.3V
±
5%
Dedicated output supply voltage (V
DDQ
): 1.9V typical
HSTL-compatible I/O interface with dedicated input reference voltage (V
REF
): 0.85V typical
Register - Latch (R-L) read operations
Late Write (LW) write operations
Conventional 16Mb or Error-Correcting (EC) 8Mb mode of operation, selectable via dedicated mode pin (M2)
Full read/write coherency
Byte Write capability
One cycle deselect
Differential input clocks (K/K)
Programmable impedance output drivers
Sleep (power down) mode via dedicated mode pin (ZZ)
JTAG boundary scan (subset of IEEE standard 1149.1)
119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
1 / 25
March 2, 2001
SONY
®
CXK77P36E160GB / CXK77P18E160GB
512K x 36 Pin Assignment (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
2
SA
SA
(5)
SA
DQc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQd
SA
NC
(1)
TMS
3
SA
SA
SA
V
SS
V
SS
V
SS
SBWc
V
SS
V
REF
V
SS
SBWd
V
SS
V
SS
V
SS
M1
(3)
SA
TDI
4
NC
NC
V
DD
ZQ
SS
G
(6)
NC
NC
V
DD
K
K
SW
SA
SA
V
DD
SA
TCK
5
SA
SA
SA
V
SS
V
SS
V
SS
SBWb
V
SS
V
REF
V
SS
SBWa
V
SS
V
SS
V
SS
M2
(4)
SA
TDO
6
SA
SA
SA
DQb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQa
SA
NC
(1)
RSVD
(2)
Preliminary
7
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
Notes:
1. Pad Locations 2T and 6T are true no-connects. However, they are defined as SA address inputs in x18 LW SRAMs.
2. Pad Location 6U must be left unconnected. It is used by Sony for internal test purposes.
3. Pad Location 3R is defined as an M1 mode pin in LW SRAMs. However, it must be tied “high” in this device.
4. Pad Location 5R is defined as an M2 mode pin in this device. It must be tied “high” or “low”. When M2 is tied
“high”, this device functions as a conventional 16Mb R-L SRAM. When M2 is tied “low”, this device functions
as an Error-Correcting 8Mb R-L SRAM.
5. Pad Location 2B is defined as an SA address input in 16Mb LW SRAMs. However, it functions as a conventional
SA address input in this device only when M2 is tied “high”. It is ignored in this device when M2 is tied “low”.
6. Pad Location 4F is defined as a G output enable input in LW SRAMs. However, it must be tied “low” in this device.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
2 / 25
March 2, 2001
SONY
®
CXK77P36E160GB / CXK77P18E160GB
1M x 18 Pin Assignment (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQb
NC
(1b)
V
DDQ
NC
(1b)
DQb
V
DDQ
NC
(1b)
DQb
V
DDQ
DQb
NC
(1b)
NC
NC
V
DDQ
2
SA
SA
(5)
SA
NC
(1b)
DQb
NC
(1b)
DQb
NC
(1b)
V
DD
DQb
NC
(1b)
DQb
NC
(1b)
DQb
SA
SA
TMS
3
SA
SA
SA
V
SS
V
SS
V
SS
SBWb
V
SS
V
REF
V
SS
V
SS
V
SS
V
SS
V
SS
M1
(3)
SA
TDI
4
NC
NC
V
DD
ZQ
SS
G
(6)
NC
NC
V
DD
K
K
SW
SA
SA
V
DD
NC
(1a)
TCK
5
SA
SA
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
REF
V
SS
SBWa
V
SS
V
SS
V
SS
M2
(4)
SA
TDO
6
SA
SA
SA
DQa
NC
(1b)
DQ6a
NC
(1b)
DQa
V
DD
NC
(1b)
DQa
NC
(1b)
DQa
NC
(1b)
SA
SA
RSVD
(2)
Preliminary
7
V
DDQ
NC
NC
NC
(1b)
DQa
V
DDQ
DQa
NC
(1b)
V
DDQ
DQa
NC
(1b)
V
DDQ
NC
(1b)
DQa
NC
ZZ
V
DDQ
Notes:
1a. Pad Location 4T is a true no-connect. However, it is defined as an SA address input in x36 LW SRAMs.
1b. Pad Locations 2D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 1K, 6K, 2L, 7L, 6M, 2N, 7N, 1P, and 6P are true no-connects.
However, they are defined as DQ data inputs / outputs in x36 LW SRAMs.
2. Pad Location 6U must be left unconnected. It is used by Sony for internal test purposes.
3. Pad Location 3R is defined as an M1 mode pin in LW SRAMs. However, it must be tied “high” in this device.
4. Pad Location 5R is defined as an M2 mode pin in this device. It must be tied “high” or “low”. When M2 is tied
“high”, this device functions as a conventional 16Mb R-L SRAM. When M2 is tied “low”, this device functions
as an Error-Correcting 8Mb R-L SRAM.
5. Pad Location 2B is defined as an SA address input in 16Mb LW SRAMs. However, it functions as a conventional
SA address input in this device only when M2 is tied “high”. It is ignored in this device when M2 is tied “low”.
6. Pad Location 4F is defined as a G output enable input in LW SRAMs. However, it must be tied “low” in this device.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
3 / 25
March 2, 2001
SONY
®
CXK77P36E160GB / CXK77P18E160GB
Pin Description
Preliminary
Symbol
SA
DQa, DQb
DQc, DQd
Type
Input
I/O
Description
Synchronous Address Inputs - Registered on the rising edge of K.
Synchronous Data Inputs / Outputs - Registered on the rising edge of K during write operations.
Driven from the falling edge of K during read operations.
DQa - indicates Data Byte a
DQb - indicates Data Byte b
DQc - indicates Data Byte c
DQd - indicates Data Byte d
Differential Input Clocks
Synchronous Select Input - Registered on the rising edge of K.
specifies a write operation when SW = 0
SS = 0
specifies a read operation when SW = 1
specifies a deselect operation
SS = 1
Synchronous Global Write Enable Input - Registered on the rising edge of K.
specifies a write operation when SS = 0
SW = 0
specifies a read operation when SS = 0
SW = 1
Synchronous Byte Write Enable Inputs - Registered on the rising edge of K.
SBWa = 0 specifies write Data Byte a when SS = 0 and SW = 0
SBWb = 0 specifies write Data Byte b when SS = 0 and SW = 0
SBWc = 0 specifies write Data Byte c when SS = 0 and SW = 0
SBWd = 0 specifies write Data Byte d when SS = 0 and SW = 0
Asynchronous Output Enable Input - Not supported. This control pin must be tied “low”.
Asynchronous Sleep Mode Input - Asserted (high) forces the SRAM into low-power mode.
Read Operation Protocol Select 1 - This mode pin must be tied “high” to select Register - Latch
read operations.
Read Operation Protocol Select 2 - This mode pin must be tied “high” or “low”.
M2 = 0
selects Error-Correcting 8Mb R-L functionality
M2 = 1
selects conventional 16Mb R-L functionality
Output Impedance Control Resistor Input
3.3V Core Power Supply - Core supply voltage.
Output Power Supply - Output buffer supply voltage.
Input Reference Voltage - Input buffer threshold voltage.
Ground
K, K
SS
Input
Input
SW
Input
SBWa, SBWb,
SBWc, SBWd
Input
G
ZZ
M1
M2
Input
Input
Input
Input
ZQ
V
DD
V
DDQ
V
REF
V
SS
TCK
TMS
TDI
TDO
RSVD
NC
Input
Input
Input
Input
Output
JTAG Clock
JTAG Mode Select
JTAG Data In
JTAG Data Out
Reserved - This pin is used for Sony test purposes only. It must be left unconnected.
No Connect - These pins are true no-connects, i.e. there is no internal chip connection to these
pins. They can be left unconnected or tied directly to V
DD
, V
DDQ
, or V
SS
.
4 / 25
March 2, 2001
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
SONY
®
CXK77P36E160GB / CXK77P18E160GB
Preliminary
•
Clock Truth Table
K
X
L
→
H
L
→
H
L
→
H
L
→
H
L
→
H
ZZ
H
L
L
L
L
L
SS
(t
n
)
X
H
L
L
L
L
SW
(t
n
)
X
X
H
L
L
L
SBWx
(t
n
)
X
X
X
L
X
H
Operation
Sleep (Power Down) Mode
Deselect
Read
Write All Bytes
Write Bytes With SBWx = L
Abort Write
DQ
(t
n
)
Hi - Z
Hi - Z
Q(t
n
)
Hi - Z
Hi - Z
Hi - Z
DQ
(t
n+1
)
Hi - Z
X
X
D(t
n
)
D(t
n
)
X
•
Dynamic M2 Mode Pin State Changes
Although M2 is defined as a static input (that is, it must be tied “high” or “low” at power-up), in some instance (such as
during device testing) it may be desirable to change its state dynamically (that is, without first powering off the SRAM)
while preserving the contents of the memory array. If so, the following criteria must be met:
1. At least two (2) consecutive deselect operations must be initiated prior to changing the state of M2, to ensure that the
most recent read or write operation completes successfully.
2. At least thirty-two (32) consecutive deselect operations must be initiated after changing the state of M2 before any read
or write operations can be initiated, to allow the SRAM sufficient time to recognize the change in state.
•
Sleep (Power Down) Mode
Sleep (power down) mode is provided through the asynchronous input signal ZZ. When ZZ is asserted (high), the output
drivers will go to a Hi-Z state, and the SRAM will begin to draw standby current. Contents of the memory array will be
preserved. An enable time (t
ZZE
) must be met before the SRAM is guaranteed to be in sleep mode, and a recovery time
(t
ZZR
) must be met before the SRAM can resume normal operation.
•
Programmable Impedance Output Drivers
These devices have programmable impedance output drivers. The output impedance is controlled by an external resistor,
RQ, connected between the SRAM’s ZQ pin and V
SS
, and is equal to one-fifth the value of this resistor, nominally. See
the DC Electrical Characteristics section for further information.
The output impedance is updated whenever the output drivers are in a Hi-Z state. Consequently, impedance updates will
occur during write and deselect operations. At power up, 8192 clock cycles followed by an impedance update via one of
the three methods described above are required to ensure that the output impedance has reached the desired value. After
power up, periodic impedance updates via write or deselect operations are also required to ensure that the output imped-
ance remains within specified tolerances.
•
Power-Up Sequence
For reliability purposes, Sony recommends that power supplies power up in the following sequence: V
SS
, V
DD
, V
DDQ
,
V
REF
, and Inputs. V
DDQ
should never exceed V
DD
. If this power supply sequence cannot be met, a large bypass diode
may be required between V
DD
and V
DDQ
. Please contact Sony Memory Application Department for further information.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
5 / 25
March 2, 2001
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