CXL1510M
CCD Delay Line for Multi System
Description
The CXL1510M is an IC developed for use in
conjunction with Y/C signal processing ICs for multi
systems. This CCD delay line provides the comb
filter output for eliminating the chrominance signal
cross talk and 1H delay output for luminance signals.
Features
•
Single power supply (5V)
•
Built-in quadruple progression PLL circuit
•
Comb filter characteristics selectable
•
Delay time for 1H delay output selectable
•
Built-in peripheral circuits
•
Positive phase signal input, positive phase signal output
Functions
•
Comb filter output
•
1H delay output for luminance signal
•
Clock driver
•
Autobias circuit
•
Input clamp circuit (for luminance signals)
•
Center bias circuit (for chrominance signals)
•
Sample-and-hold circuit
•
Quadruple progression PLL circuit
•
Luminance signal delay time/comb filter characteristics selection circuit
•
Clock buffer output circuit
Absolute Maximum Ratings
(Ta = 25°C)
•
Supply voltage
V
DD
+6
V
•
Operating temperature
Topr –10 to +60 °C
•
Storage temperature
Tstg –55 to +150 °C
•
Allowable power dissipation P
D
500
mW
Recommended Operating Voltage
(Ta = 25°C)
V
DD
5V ± 5%
Structure
CMOS-CCD
24 pin SOP (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94804-ST
CXL1510M
Recommended Clock Conditions
(Ta = 25*C)
•
Input clock amplitude
V
CLK
0.3Vp-p to 1.0Vp-p (0.5Vp-p Typ.)
•
Clock frequency
f
CLK
3.579545MHz
•
Input clock waveform
sine wave
Input Signal Amplitude
Vsig
350mVp-p (Typ.), 575mVp-p (Max.)
Block Diagram and Pin Configuration
(Top View)
PCOUT
CONT1
C-OUT
AB-C
(NC)
(NC)
Vss
VCOIN
AB-P
(NC)
24
23
22
21
20
19
18
17
16
15
14
13
PLL
fsc buffer
Selector 1
Timing
D
Output
circuit (S/H)
Autobias
circuit (C)
1H/2H + D
Driver
φ1
Autobias
circuit (Y)
Driver
φ2
Bias circuit
Bias circuit
Selector 2
Clamp circuit
1H
Output
circuit (S/H)
1
2
3
4
5
6
7
8
9
10
11
12
CONT2
(NC)
V
DD
C-IN1
(NC)
(NC)
Y-IN
Vss
Y-OUT
C-IN2
–2–
(NC)
CLK
Vss
fsc
CXL1510M
Description of Functions
The CXL1510M enables the chrominance comb filter characteristics and luminance signal delay time to be
selected using the control 1 and control 2 statuses.
CONT1 CONT2 Mode (typical example)
L
L
H
H
L
H
L
H
PAL/GBI
PAL/M
—
NTSC/M
Chrominance comb filter
characteristics
2H + 12 (1832bit)
2H (1820bit)
—
1H (910bit)
Luminance signal delay time
(number of CCD bits)
1H + 6 (914bit)
1H (908bit)
—
1H (908bit)
CONT1/CONT2 Input Level
L/H
L
H
Min.
—
2.0
Typ.
0
5.0
Max.
0.5
6.0
Unit
V
• fsc Output Pin
The buffer output of the clock input from the CLK pin is provided at the fsc output pin. Since a pull-up resistor
is contained inside the IC, the supply voltage is produced during open, and the output is stopped. Connect a
2.2kΩ pull-down resistor when the fsc output is to be used.
<When in use>
<When not in use>
fsc
fsc
V
DD
2.2k
–4–
CXL1510M
Electrical Characteristics
(Ta = 25°C, V
DD
= 5V, f
CLK
= 3.579545MHz, V
CLK
= 500mVp-p sine wave)
See Electrical Characteristics Measurement Circuit
Item
Symbol
IDD1
Supply
current
IDD2
IDD3
—
Measurement
condition
1
b
b
b
SW condition
2
b
b
b
3
b
b
b
4
a
a
b
5
a
b
b
6
7
8
Min.
Typ.
Max.
Unit
Note
a — —
a — —
a — —
35
50
mA
1
Chrominance Signal Characteristics
(No signals input to Y-IN)
Item
Low
frequency
gain
Symbol
GLC1
GLC2
GLC3
FC1
Frequency
response
FC2
FC3
LIC1
Linearity
LIC2
LIC3
Comb
depth min.
gain
CCD1
CCD2
CCD3
SNC1
SN ratio
SNC2
SNC3
CPC1
Coupling
level
Delay
time
CPC2
CPC3
DC
(See Note 8)
(See Note 7)
50% white
video signal
(See Note 5)
(See Note 4)
(See Note 3)
(See Note 2)
Measurement
condition
1
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
b
b
b
a
SW condition
2
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
b
b
b
b
3
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
4
a
a
b
a
a
b
a
a
b
a
a
b
a
a
b
a
a
b
5
6
7
8
b
b
b
b
b
b
b
b
b
b
b
b
d
d
d
b
b
b
a
—
230
—
ns
8
10
50
mVrms
7
52
56
dB
6
–40
–25
dB
5
–0.3
0
0.3
dB
4
–2.7
–2
–1.7
–1
0
0
dB
3
–2
0
2
dB
2
Min.
Typ.
Max.
Unit
Note
a — a
b — a
b — a
a — a
b — a
b — a
a — a
b — a
b — a
a — a
b — a
b — a
a — a
b — a
b — a
a — a
b — a
b — a
b — — — a
–5–
Embedded System
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