PRELIMINARY TECHNICAL DATA
a
®
ADuC842 MicroConverter , 12- Bit ADCs and DACs
with Embedded Hi-Speed 62KB FLASH MCU
Preliminary Technical Data
FEATURES
PIN COMPATABLE
Upgrade to ADuC812/ADuC832
INCREASED PERFORMANCE
Single Cycle 16MIPS 8052 core
High Speed 400kSPS 12-Bit ADC
INCREASED MEMORY
62Kbytes On-Chip Flash/EE Program Memory
4KBytes On-Chip Flash/EE Data Memory
In circuit re-programmable
Flash/EE, 100 Yr Retention, 100 Kcycles Endurance
2304 Bytes On-Chip Data RAM
SMALLER PACKAGE
Available in 8mm x 8mm Chip Scale Package
Also available in 52 pin PQFP - pin compatable with
ADuC812/ADuC831
ANALOG I/O
8-Channel, 400kSPS High Accuracy, 12-Bit ADC
On-Chip, 20 ppm/
o
C Voltage Reference
DMA Controller, High-Speed ADC-to-RAM capture
Two 12-Bit Voltage Output DACs
Dual Output PWM-SD DACs
On-Chip Temperature Monitor Function
8051 Based Core
8051-Compatible Instruction Set (16.7 MHz Max)
High performance Single Cycle Core*
32kHz Ext Crystal,On-Chip Programmable-PLL
12 Interrupt Sources, Two Priority Levels
Dual Data Pointers, Extended 11-bit Stack Pointer
On-Chip Peripherals
Time Interval Counter (TIC)
UART, I2C and SPI
®
Serial I/O
Watchdog Timer (WDT),
Power Supply Monitor (PSM)
Power
Normal: 6mA @ 5 V (Core CLK = 2.098 MHz)
Power-Down: 15µA @ 3 V
Development Tools
Low Cost, comprehensive development system
incorporating non-intrusive single pin emulation
IDE based, assembly and C source debug
APPLICATIONS
Optical Networking - Laser Power Control
Basestation Systems
Precision Instrumentation, Smart Sensors
Transient Capture Systems
DAS and Communications Systems
MicroConverter is a registered trademark of Analog Devices, Inc.
SPI is a registered trademark of Motorola Inc.
* 68% of insturctions completed in one or two clock cycles
ADuC842
FUNCTIONAL
ADuC842
12-B T
I
D
AC
BU F
D AC
BLOCK
DIAGRAM
A D C0
A D C1
.
.
.
MU X
T/H
4 0 0 K SP S
12 -B IT A D C
12-B T
I
D
AC
16-BIT
Σ ∆
DAC
BU F
D AC
A D C5
A D C6
A D C7
H AR D W AR E
C AL IBR A TIO N
16-BIT
Σ ∆
DAC
P WM 0
MU X
PW M1
16-BIT
PW
M
16-BIT
PWM
TEM P
S EN SO R
P LL
16 MIP S 8 0 51 -B AS ED MC U WITH AD D IT IO NA L
PE RIP H ER AL S
6 2 K BY TES FL A SH /EE PR O GR AM M EMO RY
4 KB YTES FLA SH /E E DA TA MEM O R Y
2 3 04 BY TE S US ER R AM
3
×
1 6 B IT TIM ER S
1
×
R E AL TIM E C L O C K
IN TE R N AL
BA N DG AP
V R EF
OSC
PO W ER S UP PL Y M O N
WA TC H DO G TIME R
U A RT , I2 C AN D SPI
S ER IA L I/O
4
×
P AR A L LE L
P O R TS
VR E F
X TAL 1
XT AL 2
GENERAL DESCRIPTION
The ADuC842 is a complete smart transducer front-end, inte-
grating a high-performance self calibrating multichannel ADC,
dual DAC and an optimized single cycle 16MHz 8-bit
MCU(8051 instruction set compatible) on a single chip.
The device operates from a 32 kHz crystal with an on-chip PLL
generating a high-frequency clock of 16.77MHz. This clock is,
in turn, routed through a programmable clock divider from
which the MCU core clock operating frequency is generated.
The microcontroller is an optimized 8052 core offering up to 16
MIPS peak performance. 62 Kbytes of nonvolatile Flash/EE
program memory are provided on-chip. 4 Kbytes of nonvolatile
Flash/EE data memory, 256 bytes RAM and 2 KBytes of ex-
tended RAM are also integrated on-chip.
The ADuC842 also incorporates additional analog functionality
with two 12-bit DACs, power supply monitor, and a bandgap
reference. On-chip digital peripherals include two 16-bit
Σ∆
DACs, dual output 16-bit PWM, watchdog timer, time interval
counter, three timers/counters, and three serial I/O ports (SPI,
I2C and UART).
On the ADuC812 and ADuC832 the I2C and SPI interfaces
shared some of the same pins. For backwards compatability
this is also the case for the ADuC842. However, there is also
the option to allow SPI operate separately on P3.3, P3.4 and
P3.5 while I2C uses the standard pins. The I2C interface has
also been enhanced to offer repeated start, general call and
quad addressing.
On-chip factory firmware supports in-circuit serial download and
debug modes (via UART), as well as single-pin emulation mode
via the EA pin. A functional block diagram of the ADuC842 is
shown above.
The part is specified for 3V and 5V operation with a maximum
operating frequency of 16.777MHz.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2003
REV. PrB
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
ADuC842–SPECIFICATIONS
1
T (AV
to 5.5V. V
= 2.5 V Internal Reference, Fcore = 16.777 MHz, All specifications = T
REF
A
PRELIMINARY TECHNICAL DATA
DD
= DV
DD
= 2.7V to 3.3V or 4.5V
MIN
to T
MAX
, unless otherwise noted.)
Test Conditions/Comments
Parameter
ADC CHANNEL SPECIFICATIONS
DC ACCURACY
2,3
Resolution
Integral Nonlinearity
Differential Nonlinearity
Integral Nonlinearity
9
Differential Nonlinearity
9
Code Distrbution
CALIBRATED ENDPOINT ERRORS
4,5
Offset Error
Offset Error Match
Gain Error
Gain Error Match
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
6
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Channel-to-Channel Crosstalk
7
ANALOG INPUT
Input Voltage Ranges
Leakage Current
Input Capacitance
TEMPERATURE SENSOR
8
Voltage Output at 25°C
Voltage TC
Accuracy
Accuracy
DAC CHANNEL SPECIFICATIONS
Internal Buffer Enabled
DC ACCURACY
10
Resolution
Relative Accuracy
Differential Nonlinearity
11
Offset Error
Gain Error
Gain Error
Mismatch
V
DD
= 5 V
V
DD
= 3 V
Unit
f
SAMPLE
= 147 kHz,
12
±1
±0.3
±0.9
±0.25
±1.5
+1.5/-0.9
1
±2
±1
±2
–85
12
±1
±0.3
±0.9
±0.25
±1.5
+1.5/-0.9
1
±3
±1
±3
–85
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
max
typ
max
typ
max
max
typ
2.5V Internal Reference
2.5V Internal Reference
1V External Reference
1V External Reference
ADC Input is a DC Voltage
LSB max
LSB typ
LSB max
dB typ
f
IN
= 10 kHz Sine Wave
f
SAMPLE
= 147 kHz
71
–85
–85
–80
0 to V
REF
±1
32
650
–2.0
±3
±1.5
71
–85
–85
–80
0 to V
REF
±1
32
650
–2.0
±3
±1.5
dB
dB
dB
dB
typ
typ
typ
typ
Volts
µA max
pF typ
mV typ
mV/°C typ
°C typ
°C typ
Internal 2.5V V
REF
External 2.5V V
REF
DAC Load to AGND
R
L
= 10kΩ, C
L
= 100 pF
12
±3
-1
±50
±1
±1
0.5
0 to V
REF
0 to V
DD
0.5
50
15
10
12
±3
-1
±1/2
±50
±1
±1
0.5
0 to V
REF
0 to V
DD
0.5
50
15
10
Bits
LSB typ
LSB max
±1/2
mV max
% max
% typ
% typ
V typ
V typ
Ω
typ
µA typ
µs typ
nV sec typ
Guaranteed 12-Bit Monotonic
LSB typ
V
REF
Range
AV
DD
Range
VREF Range
% of Full-Scale on DAC1
DAC V
REF
= 2.5V
DAC V
REF
= V
DD
ANALOG OUTPUTS
Voltage Range_0
Voltage Range_1
Output Impedance
I
SINK
DAC AC CHARACTERISTICS
Voltage Output Settling Time
Digital-to-Analog Glitch Energy
Full-Scale Settling Time to
Within 1/2 LSB of Final Value
1 LSB Change at Major Carry
–2–
REV. PrB
PRELIMINARY TECHNICAL DATA
ADuC842
Parameter
V
DD
= 5 V
V
DD
= 3 V
Unit
Test Conditions/Comments
DAC CHANNEL SPECIFICATIONS
12,13
Internal Buffer Disabled
DC ACCURACY
10
Resolution
Relative Accuracy
Differential Nonlinearity
11
Offset Error
Gain Error
Gain Error Mismatch
ANALOG OUTPUTS
Voltage Range_0
REFERENCE INPUT/OUTPUT
REFERENCE OUPUT
14
Output Voltage (V
REF
)
Accuracy
Power Supply Rejection
Reference Temperature Coefficient
Internal V
REF
Power-On Time
EXTERNAL REFERNCE INPUT
15
Voltage Range (V
REF
)
9
Input Impedance
Input Leakage
POWER SUPPLY MONITOR (PSM)
DV
DD
Trip Point Selection Range
DV
DD
Power Supply Trip Point
Accuracy
WATCH DOG TIMER (WDT)
9
Time-out Period
2.63
4.37
Vmin
Vmax
Four Trip Points Selectable in
This Range Programmed via
TPD1–0 in PSMCON
12
±3
-1
±1/2
±10
±1
0.5
0 to V
REF
12
±3
-1
±1/2
±10
±1
0.5
0 to V
REF
Bits
LSB typ
LSB max
LSB typ
mV max
% typ
% typ
V typ
Guaranteed 12-Bit Monotonic
V
REF
Range
VREF Range
% of Full-Scale on DAC1
DAC V
REF
= 2.5V
2.5
±2.5
47
±20
80
0.1
V
DD
20
10
2.5
±2.5
57
±20
80
0.1
V
DD
20
10
V
% max
dB typ
ppm/°C typ
ms typ
V min
V max
kΩ typ
µA max
Of V
REF
measured at the C
REF
pin
Internal Band Gap Deselected via
ADCCON1.6
±3.5
0
2000
0
2000
% max
ms min
ms max.
Nine Time-out Periods
Selectable in This Range
FLASH/EE MEMORY RELIABILITY
CHARACTERISTICS
16
Endurance
17
100,000
Data Retention
18
100
DIGITAL INPUTS
Input High Voltage (V
INH
)
2.4
Input Low Voltage (V
INL
)
0.8
Input Leakage Current (Port 0,1, EA) ±10
±1
Logic 1 Input Current
(All Digital Inputs)
±10
±1
Logic 0 Input Current (Port 2, 3)
–80
–40
Logic 1-0 Transition Current (Port 2, 3) –700
–400
CRYSTAL OSCILLATOR
Logic Inputs, XTAL1 Only
VINL, Input Low Voltage
VINH, Input High Voltage
REV. PrB
100,000
100
Cycles min
Years min
V min
V max
µA max
µA typ
µA
µA
µA
µA
µA
µA
max
typ
max
typ
max
typ
±1
V
IN
= 0 V or V
DD
V
IN
= 0 V or V
DD
V
IN
= V
DD
V
IN
= V
DD
V
IL
= 0 V
V
IL
= 2 V
V
IL
= 2 V
±1
–40
–400
0.8
3.5
0.4
2.5
–3–
V typ
V typ
ADuC842–SPECIFICATIONS
1
Parameter
XTAL1 Input Capacitance
XTAL2 Output Capacitance
MCU Clock Rate
DIGITAL OUTPUTS
Output High Voltage (V
OH
)
V
DD
=5V
18
18
16.777216
2.4
4.0
Output Low Voltage (V
OL
)
ALE, Ports 0 and 2
Port 3
SCLOCK/SDATA
V
DD
=3V
18
18
16.777216
2.4
2.6
PRELIMINARY TECHNICAL DATA
Units
pF typ
pF typ
MHz max
V min
V typ
V
DD
= 4.5 V
I
SOURCE
= 80
V
DD
= 2.7 V
I
SOURCE
= 20
I
SINK
I
SINK
I
SINK
I
SINK
=
=
=
=
to 5.5 V
µA
to 3.3 V
µA
Test Conditions
0.4
0.2
0.4
0.4
0.4
0.2
0.4
0.4
V max
V typ
Vmax
Vmax
1.6 mA
1.6 mA
4 mA
8 mA
Floating State Leakage Current
Floating State Output Capacitance
±10
±1
10
±10
±1
10
µA max
µA typ
pF typ
Core CLK = 16MHz
START UP TIME
At Power-On
500
From Idle Mode
100
From Power-Down Mode
Wakeup with INT0 Interrupt
150
150
Wakeup with SPI/I
2
C Interrupt
Wakeup with External RESET
150
After External RESET in Normal Mode 3
After WDT Reset in Normal Mode 3
POWER REQUIREMENTS
Power Supply Voltages
AV
DD
/ DV
DD
- AGND
19,20
500
100
400
400
400
3
3
ms typ
µs typ
ms
ms
ms
ms
ms
typ
typ
typ
typ
typ
Controlled via WDCON SFR
2.7
3.3
4.5
5.5
V
V
V
V
min.
max.
min.
max.
AV
DD
/ DV
DD
= 3V nom.
AV
DD
/ DV
DD
= 5V nom.
Power Supply Currents Normal Mode
D
VDD
Current
9
A
VDD
Current
9
D
VDD
Current
A
VDD
Current
Power Supply Currents Idle Mode
D
VDD
Current
9
A
VDD
Current
9
D
VDD
Current
9
A
VDD
Current
9
12
1.4
25
21
1.4
6
1.4
n/a
n/a
n/a
mA
mA
mA
mA
mA
typ
max
max
typ
max
Fcore = 8 MHz (CD=3)
Fcore = 16 MHz (CD=0)
5
0.11
11
10
0.11
2.5
0.11
n/a
n/a
n/a
mA
mA
mA
mA
mA
typ
typ
max
typ
typ
Fcore = 8 MHz (CD=3)
Fcore =16 MHz (CD=0)
Power Supply Currents Power Down Mode
3
A
VDD
Current
D
VDD
Current
35
25
120
Typical Additional Power Supply Currents
PSM Peripheral
ADC
DAC
For any Core CLK
2.5
15
12
120
uA
uA
uA
uA
typ
max
typ
typ
osc off
osc on
AVDD = DVDD = 5V
50
1.5
150
–4–
uA typ
mA typ
uA typ
REV. PrB
PRELIMINARY TECHNICAL DATA
ADuC842
NOTES
1
Temperature Range -40ºC to +85ºC.
2
ADC Linearity is guaranteed during normal MicroConverter Core operation.
3
ADC LSB Size = Vref / 2^12 i.e for Internal Vref=2.5V, 1LSB = 610uV and for External Vref =1V, 1LSB = 244uV.
4
Offset and Gain Error and Offset and Gain Error Match are measured after factory calibration.
5
Based on external ADC system components the user may need to execute a system calibration to remove additional external channel errors
and achieve these specifications.
6
SNR calculation includes distortion and noise components.
7
Channel to Channel Crosstalk is measured on adjacent channels.
8
The Temperature Monitor will give a measure of the die temperature directly, air temperature can be inferred from this result.
9
These numbers are not production tested but are guaranteed by Design and/or Characterization data on production release.
10
DAC linearity is calculated using :
reduced code range of 48 to 4095, 0 to Vref range.
reduced code range of 48 to 3945, 0 to V
DD
range.
DAC Output Load = 10K Ohms and 100 pF.
11
DAC Differential NonLinearity specified on 0 to Vref and 0 to Vdd ranges
12
DAC specification for output impedance in the unbuffered case depends on DAC code
13
DAC specifications for Isink, voltage output settling time and digital-to-analog glitch engergy depend on external buffer implementation in
unbuffered mode.
14
Measured with Vref and Cref pins decoupled with 0.1µF capacitors to graound. Power-up time for the Internal Reference will be determined
by the value of the decoupling capacitor chosen for both the Vref and Cref pins.
15
When using an External Reference device, the internal bandgap reference input can be bypassed by setting the ADCCON1.6 bit. In this
mode the Vref and Cref pins need to be shorted together for correct operation.
16
Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and the Flash/EE data memory.
17
Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at -40ºC, +25ºC, and +85ºC, typical endurance at
25ºC is 700 Kcycles.
18
Retention lifetime equivalent at junction temperature (Tj) = 55ºC as per JEDEC Std. 22 method A117. Retention lifetime based on an
activation energy of 0.6eV will derate with junction temperature as shown in Figure 27 in the Flash/EE Memory description section of this
data sheet.
19
Power Supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions:
Normal Mode:
Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal
software loop.
Idle Mode:
Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0=1, Core
Execution suspended in idle mode.
Power-Down Mode: Reset = 0.4 V, All Port 0 pins = 0.4 V, All other digital I/O and Port 1 pins are open circuit, Core Clk changed
via CD bits in PLLCON, PCON.0=1, Core Execution suspended inpower-down mode, OSC turned ON or OFF via
OSC_PD bit (PLLCON.7) in PLLCON SFR
20
D
VDD
power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program
or erase cycle.
Specifications subject to change without notice.
REV. PrB
–5–
Analogue and Mixed Signal
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