Philips Semiconductors
Product specification
Hex inverter
74HC04; 74HCT04
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT762-1
14 terminals; body 2.5 x 3 x 0.85 mm
D
B
A
A
A1
E
c
terminal 1
index area
detail X
terminal 1
index area
e
2
L
e1
b
6
v
M
C A B
w
M
C
y1 C
C
y
1
Eh
14
7
e
8
13
Dh
0
9
X
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
(1)
max.
1
A1
0.05
0.00
b
0.30
0.18
c
0.2
D
(1)
3.1
2.9
Dh
1.65
1.35
E
(1)
2.6
2.4
Eh
1.15
0.85
e
0.5
e1
2
L
0.5
0.3
v
0.1
w
0.05
y
0.05
y1
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
OUTLINE
VERSION
SOT762-1
REFERENCES
IEC
---
JEDEC
MO-241
JEITA
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
2003 Jul 23
18
Philips Semiconductors
Product specification
Hex inverter
FEATURES
•
Complies with JEDEC standard no. 8-1A
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•
Specified from
−40
to +85
°C
and
−40
to +125
°C.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
6.0 ns.
DESCRIPTION
74HC04; 74HCT04
The 74HC/HCT04 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A. The 74HC/HCT04 provide six inverting
buffers.
TYPICAL
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. For 74HC04: the condition is V
I
= GND to V
CC
.
For 74HCT04: the condition is V
I
= GND to V
CC
−
1.5 V.
FUNCTION TABLE
See note 1.
INPUT
nA
L
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
OUTPUT
nY
H
L
PARAMETER
propagation delay nA to nY
input capacitance
power dissipation capacitance per gate notes 1 and 2
CONDITIONS
HC04
C
L
= 15 pF; V
CC
= 5 V
7
3.5
21
8
3.5
24
HCT04
ns
pF
pF
UNIT
2003 Jul 23
2
FPGA/CPLD
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