72V245L20TFG datasheet, PDF - EEWORLD Datasheet

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72V245L20TFG: DescriptionFIFO, 4KX18, 12ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, STQFP-64; Categorystorage storage; File Size401KB，25 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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72V245L20TFG Overview

FIFO, 4KX18, 12ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, STQFP-64

72V245L20TFG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	QFP
package instruction	LFQFP, QFP64,.47SQ,20
Contacts	64
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	12 ns
Other features	EASILY EXPANDABLE IN DEPTH AND WIDTH
Maximum clock frequency (fCLK)	50 MHz
period time	20 ns
JESD-30 code	S-PQFP-G64
JESD-609 code	e3
length	10 mm
memory density	73728 bit
Memory IC Type	OTHER FIFO
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	64
word count	4096 words
character code	4000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4KX18
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP64,.47SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.005 A
Maximum slew rate	0.03 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	10 mm
Base Number Matches	1

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3.3 VOLT CMOS SyncFIFO

256 x 18, 512 x 18, 1,024 x 18,

2,048 x 18, and 4,096 x 18

IDT72V205, IDT72V215,

IDT72V225, IDT72V235,

IDT72V245

FEATURES:

•

256 x 18-bit organization array (IDT72V205)

512 x 18-bit organization array (IDT72V215)

1,024 x 18-bit organization array (IDT72V225)

2,048 x 18-bit organization array (IDT72V235)

4,096 x 18-bit organization array (IDT72V245)

10 ns read/write cycle time

5V input tolerant

IDT Standard or First Word Fall Through timing

Single or double register-buffered Empty and Full flags

Easily expandable in depth and width

Asynchronous or coincident Read and Write Clocks

Asynchronous or synchronous programmable Almost-Empty

and Almost-Full flags with default settings

Half-Full flag capability

Output enable puts output data bus in high-impedance state

High-performance submicron CMOS technology

Available in a 64-lead thin quad flatpack (TQFP/STQFP)

•

Industrial temperature range (–40°C to +85°C) is available

Green parts available, see ordering information

DESCRIPTION:

The IDT72V205/72V215/72V225/72V235/72V245 are functionally com-

patible versions of the IDT72205LB/72215LB/72225LB/72235LB/72245LB,

designed to run off a 3.3V supply for exceptionally low power consumption.

These devices are very high-speed, low-power First-In, First-Out (FIFO)

memories with clocked read and write controls. These FIFOs are applicable

for a wide variety of data buffering needs, such as optical disk controllers, Local

Area Networks (LANs), and interprocessor communication.

These FIFOs have 18-bit input and output ports. The input port is controlled

by a free-running clock (WCLK), and an input enable pin (WEN). Data is read

into the synchronous FIFO on every clock when

WEN

is asserted. The output

port is controlled by another clock pin (RCLK) and another enable pin (REN).

The Read Clock(RCLK) can be tied to the Write Clock for single clock operation

or the two clocks can run asynchronous of one another for dual-clock operation.

An Output Enable pin (OE) is provided on the read port for three-state control

of the output.

FUNCTIONAL BLOCK DIAGRAM

WEN

WCLK

D0-D17

INPUT REGISTER

OFFSET REGISTER

FF/IR

PAF

EF/OR

PAE

HF/(WXO)

WRITE CONTROL

LOGIC

FLAG

LOGIC

RAM ARRAY

256 x 18, 512 x 18

1,024 x 18, 2,048 x 18

4,096 x 18

WRITE POINTER

WXI

(HF)/WXO

RXI

RXO

READ POINTER

READ CONTROL

LOGIC

EXPANSION LOGIC

OUTPUT REGISTER

RESET LOGIC

Q0-Q17

RCLK

REN

4294 drw 01

IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

MARCH 2013

DSC-4294/7

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