CXP88616/88624
CMOS 8-bit Single Chip Microcomputer
Description
The CXP88616/88624 is a CMOS 8-bit micro-
computer which consists of A/D converter, serial
interface, timer/counter, time base timer, high
precision timing pattern generation circuits, PWM
output, VISS/ VASS circuit, remote control receiving
circuit, VSYNC separator and the measurement
circuit which measure signals of capstan FG
amplifier and drum FG/PG amplifier and other servo
systems, as well as basic configurations like 8-bit
CPU, ROM, RAM and I/O port. They are integrated
into a single chip.
Also, CXP88616/88624 provides sleep/stop function
which enables to lower power consumption.
100 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Features
•
A wide instruction set (213 instructions) which cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
•
Minimum instruction cycle
250ns at 16MHz operation
•
Incorporated ROM capacity
16K bytes (CXP88616)
24K bytes (CXP88624)
•
Incorporated RAM capacity
672 bytes (including PPG RAM)
•
Peripheral function
— A/D converter
8 bits, 14 channels, successive approximation system
(Conversion time of 20µs/16MHz)
— Serial interface
Incorporated 8-bit, 8-stage FIFO for data
(Auto transfer for 1 to 8 bytes), 1 channel
— Timer
8-bit timer/counter, 2 channels
19-bit time base timer
— High precision timing pattern generation PPG 19 pins 32-stage programmable circuit
RTG 5 pins, 1 channel
5-bit, 8-satge FIFO (RECCTL control), 1channel
— PWM/DA gate output
12 bits, 2 channels (Repetitive frequency 62.5kHz/16MHz)
DA gate pulse output, 13 bits, 2 channels
— Analog signal input circuit
Capstan FG amplifier circuit
Drum FG amplifier circuit
Drum PG amplifier circuit
PBCTL amplifier circuit
— CTL write/rewrite circuit
Recording current control circuit
— Servo input control
Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit
Incorporated 26-bit and 8-stage FIFO
— VISS/VASS circuit
Pulse duty auto detection circuit
— 32kHz timer/event counter
32kHz oscillation circuit, ultra-low speed instruction mode
— Remote control reception circuit
8-bit pulse measurement counter, 6-stage FIFO
— Tri-state output
PPG 1 pin, output 8 pins
— Pseudo HSYNC output function
— High speed head switching circuit
•
Interruption
20 factors, 15 vectors, multi-interruption possible
•
Standby mode
SLEEP/STOP
•
Package
100-pin plastic QFP
•
Piggyback/evaluation chip
CXP88800 100-pin ceramic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96108-ST
CXP88616/88624
Pin Description
Symbol
PA0/PPO0
/HGO
PA1/PPO1
to
PA7/PPO7
I/O
Output/Real-time
output/Output
Output/
Real-time output
(Port A)
8-bit output port. Data is
gated with PPO contents
by OR-gate and they are
output.
(8 pins)
(Port B)
8-bit output port. Data is
gated with PPO contents
by OR-gate and they are
output.
Tri-state control is possible.
(8 pins)
(Port C)
8-bit output port. I/O can be
set in a unit of single bits.
Data is gated with PPO or
RT contents by OR-gate
and they are output.
(8 pins)
Description
Pseudo HSYNC output pin.
PB0/PPO8
to
PB7/PPO15
Output/
Real-time output
Programmable pattern generator (PPG)
output. Functions as high precision real-
time pulse output port.
(19 pins)
PA0 can be tri-state controlled with PPG.
PC0/PPO16
to
PC2/PPO18
PC3/RTO3
to
PC7/RTO7
PD0/INT1/
NMI
PD1/RMC
PD2
PD3 /TO
DDO/SRVO
PD4/CS0
PD5/SCK0
PD6/SO0
PD7/SI0
PE0
PE1
PE2
PE3/SYNC
PE4/EXI0
PE5/EXI1
PE6/PWM0/
DAA0
PE7/PWM1/
DAA1
I/O/
Real-time output
I/O/
Real-time output
Real-time pulse generator (RTG) output.
Functions as high precision real-time
pulse output port.
(5 pins)
Input pin to request external interruption
and non-maskable interruption.
Remote control receiving circuit input pin.
I/O/Input/Input
I/O/Input
I/O
I/O/Output/Output/ (Port D)
Output
8-bit output port. I/O can be
set in a unit of single bits.
I/O/Input
(8 pins)
I/O/I/O
I/O/Output
I/O/Input
Output
Output
Input
Input/Input
Input/Input
Input/Input
Output/Output
Output/Output
Timer/counter, CTL duty detector and
servo amplifier output pin.
Serial chip select (CH0) input pin.
Serial clock (CH0) I/O pin.
Serial data (CH0) output pin.
Serial data (CH0) input pin.
(Port E)
Composite sync signal input pin.
8-bit port. Bits 2, 3, 4 and 5
External input pin for FRC capture unit.
are for inputs; bits 0, 1, 6
(2 pins)
and 7 are for outputs.
(8 pins)
PWM output pin.
(2 pins)
DA gate pulse
output pin.
(2 pins)
–4–
CXP88616/88624
Description
AN0/ANOUT
AN1 to AN3
PF0/AN4
to
PF3/AN7
PF4/AN8
to
PF7/AN11
PG0/AN12
PG1/AN13
I/O
Input/Output
Input
Input/Input
Description
Analog circuit internal
waveform output pin.
Output/Input
(Port F)
Lower 4 bits are for inputs; upper 4 bits are for
outputs. Lower 4 bits are standby release input
pins.
(8 pins)
(Port G)
2-bit input port.
(2 pins)
Analog input pin for
A/D converter.
(14 pins)
Input/Input
PH0 to PH7
Output
(Port H)
8-bit output port; N-ch open drain output of medium drive voltage (12V)
and large current (12mA).
(8 pins)
(Port I)
8-bit I/O port. I/O can be
set in a unit of single bits.
Function as standby
release input can be set in
a unit of single bits.
(8 pins)
Input pin to request
Trigger pulse input
external interruption.
pin for head
Active when falling
switching.
edge.
Input pin to request
External event input external interruption.
pin for timer/counter. Active when falling
edge.
PI0/INT0/
ENV-DET
I/O/Input
PI1/EC/
INT2
PI2 to PI7
CFG
DFG
DPG
RECCTL (+)
RECCTL (–)
CTLCIN (+)
CTLCIN (–)
CTLAMP (+)
CTLAMP (–)
CTLFAMPO
CTLSAMPI
RECCAP
VREFOUT
CTLAG
AMPV
SS
AMPV
DD
I/O/Input/Input
I/O
Input
Input
Input
I/O
Output
Input
Output
Input
I/O
Output
Output
Capstan FG input pin.
Drum FG input pin.
Drum PG input pin.
RECCTL signal output pin.
(2 pins)
PBCTL signal input pin.
(2 pins)
Connected to RECCTL (+) and RECCTL (–) with the internal switch for
playback. (2 pins)
Input PBCTL signal with capacitor coupled.
(2 pins)
PBCTL signal 1st amplifier output.
PBCTL signal 2nd amplifier input.
Capacitor connecting pin for the slope setting of the CTL writing
trapezoidal wave.
Capacitor connecting pin for the VREF level smoothing of DPG, DFG
and CFG.
Capacitor connecting pin for the CTL and AGND smoothing.
Analog signal input circuit GND pin.
Analog signal input circuit power supply pin.
–5–
京公网安备 11010802033920号
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