Latch-up Current...................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
2.5V
±
0.2V
DC Electrical Characteristics
Over the Operating Range
–10
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Leakage Current
Output Leakage Current
V
CC
Operating
Supply Current
Automatic CE Power-down
Current—TTL Inputs
Automatic CE Power-down
Current —CMOS Inputs
GND < V
I
< V
CC
GND < V
OUT
< V
CC
, Output Disabled
V
CC
= Max., f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
, V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Com’l/Ind’l
Com’l/Ind’l
Test Conditions
V
CC
= Min., I
OH
= –1.0 mA
V
CC
= Min., I
OL
= 1.0 mA
2.0
–0.3
–1
–1
Min.
2.0
0.4
V
CC
+ 0.3
0.8
+1
+1
275
100
50
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
Max. V
CC
, CE > V
CC
– 0.2V,
Com’l/Ind’l
V
IN
> V
CC
– 0.2V, or V
IN
< 0.2V, f = 0
Capacitance
[2]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= 2.5V
Max.
8
10
Unit
pF
pF
AC Test Loads and Waveforms
[3]
50Ω
OUTPUT
Z
0
= 50Ω
V
TH
= V
DD
/2
30 pF
Including all Components
R1 317Ω of Test Equipment
2.3V
90%
GND
Rise time > 1 V/ns
THÉVENIN EQUIVALENT
167Ω
OUTPUT
10%
90%
10%
Fall time:
> 1 V/ns
ALL INPUT PULSES
(a)
2.5V
Including OUTPUT
Jig and
Scope
5 pF
(b)
R2
351Ω
1.73V
(c)
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. Tested initially and after any design or process changes that may affect these parameters.
3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
DD
(2.3V). As soon as 1ms (T
power
) after reaching the
minimum operating V
DD
, normal SRAM operation can begin including reduction in V
DD
to the data retention (V
CCDR
, 1.5V) voltage.
Document #: 38-05333 Rev. *A
Page 3 of 9
[+] Feedback
CY7C1062AV25
AC Switching Characteristics
Over the Operating Range
[4]
–10
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[8, 9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Write Cycle Time
CE
1
, CE
2
, or CE
3
LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[6]
WE LOW to High-Z
[6]
Byte Enable to End of Write
7
10
7
7
0
0
7
5.5
0
3
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
CC
(typical) to the first access
[5]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
, CE
2
, or CE
3
LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[6]
OE HIGH to High-Z
[6]
Description
Min.
1
10
Max.
Unit
ms
ns
10
3
10
5
1
5
3
5
0
10
5
1
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE
1
, CE
2
, or CE
3
LOW to Low-Z
[6]
CE
1
, CE
2
, or CE
3
HIGH to High-Z
[6]
CE
1
, CE
2
, or CE
3
LOW to Power-up
[7]
CE
1
, CE
2
, or CE
3
HIGH to Power-down
[7]
Byte Enable to Data Valid
Byte Enable to Low-Z
[6]
Byte Disable to High-Z
[6]
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.1V, input pulse levels of 0 to 2.3V, and output loading of the specified
I
OL
/I
OH
and transmission line loads. Test conditions for the read cycle use output loading as shown in (a) of AC Test Loads, unless specified otherwise.
5. This part has a voltage regulator that steps down the voltage from 2.3V to 2V internally. t
power
time has to be provided initially before a read/write operation is
started.
6. t
HZOE
, t
HZCE
, t
HZWE
, t
HZBE
, and t
LZOE
, t
LZCE
, t
LZWE
, and t
LZBE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
± 200 mV from steady-state voltage.
7. These parameters are guaranteed by design and are not tested.
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE 2 HIGH, CE3 LOW, and WE LOW. The chip enables must be active and WE
must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced
to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05333 Rev. *A
Page 4 of 9
[+] Feedback
CY7C1062AV25
Data Retention Waveform
DATA RETENTION MODE
V
CC
2.3V
t
CDR
CE
V
DR
> 1.5V
2.3V
t
R
Switching Waveforms
Read Cycle No. 1
[11,12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[11,13]
ADDRESS
t
RC
CE
1
, CE
3
CE
2
t
ACE
OE
t
DOE
B
A
, B
B
, B
C
, B
D
t
LZOE
t
DBE
t
LZBE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZCE
t
HZBE
DATA VALID
t
PD
50%
I
SB
IICC
CC
t
HZOE
HIGH
IMPEDANCE
DATA OUT
Notes:
10. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
µs
or stable at V
CC(min.)
> 100
µs
11. Device is continuously selected. OE, CE, B
A
, B
B
, B
C
, B
D
= V
IL
.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
京公网安备 11010802033920号
EEWORLD
