CYD18S18V18-167BBXC datasheet, PDF

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CYD18S18V18-167BBXC: Descriptionsram 18m sync dual port 1mx18 90nm sdr com; Categorystorage storage; File Size782KB，51 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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CYD18S18V18-167BBXC Overview

sram 18m sync dual port 1mx18 90nm sdr com

CYD18S18V18-167BBXC Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	LBGA, BGA256,16X16,40
Contacts	256
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	11 ns
Other features	PIPELINED OR FLOW-THROUGH ARCHITECTURE, IT CAN ALSO OPERATES AT 1.8V
Maximum clock frequency (fCLK)	167 MHz
I/O type	COMMON
JESD-30 code	S-PBGA-B256
JESD-609 code	e1
length	19 mm
memory density	18874368 bit
Memory IC Type	DUAL-PORT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of ports	2
Number of terminals	256
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA256,16X16,40
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	1.5/1.8 V
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum standby current	0.3 A
Minimum standby current	1.4 V
Maximum slew rate	0.69 mA
Maximum supply voltage (Vsup)	1.58 V
Minimum supply voltage (Vsup)	1.42 V
Nominal supply voltage (Vsup)	1.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	19 mm
Base Number Matches	1

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FullFlex

FullFlex™ Synchronous

SDR Dual-Port SRAM

Features

• True dual-ported memory allows simultaneous access

to the shared array from each port

• Synchronous pipelined operation with Single Data Rate

(SDR) operation on each port

— SDR interface at 250 MHz

— Up to 36-Gb/s bandwidth (250 MHz * 72 bit * 2 ports)

• Selectable pipelined or flow-through mode

• 1.5V or 1.8V core power supply

• Commercial and Industrial temperature

• IEEE 1149.1 JTAG boundary scan

• Available in 484-ball PBGA Packages and 256-ball

FBGA packages

• FullFlex72 family

— 36-Mbit: 512K x 72 (CYD36S72V18)

— 18-Mbit: 256K x 72 (CYD18S72V18)

— 9-Mbit: 128K x 72 (CYD09S72V18)

— 4-Mbit: 64K x 72 (CYD04S72V18)

• FullFlex36 family

— 36-Mbit: 1M x 36 (CYD36S36V18)

— 18-Mbit: 512K x 36 (CYD18S36V18)

— 9-Mbit: 256K x 36 (CYD09S36V18)

— 4-Mbit: 128K x 36 (CYD04S36V18)

• FullFlex18 family

— 36-Mbit: 2M x 18 (CYD36S18V18)

— 18-Mbit: 1M x 18 (CYD18S18V18)

— 9-Mbit: 512K x 18 (CYD09S18V18)

— 4-Mbit: 256K x 18 (CYD04S18V18)

• Built-in deterministic access control to manage

address collisions

— Deterministic flag output upon collision detection

— Collision detection on back-to-back clock cycles

— First Busy Address readback

• Advanced features for improved high-speed data

transfer and flexibility

— Variable Impedance Matching (VIM)

— Echo clocks

— Selectable LVTTL (3.3V), Extended HSTL

(1.4V–1.9V), 1.8V LVCMOS, or 2.5V LVCMOS I/O on

each port

— Burst counters for sequential memory access

— Mailbox with interrupt flags for message passing

— Dual Chip Enables for easy depth expansion

Functional Description

The FullFlex™ Dual-Port SRAM families consist of 4-Mbit,

9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual-port static

RAMs that are high-speed, low-power 1.8V/1.5V CMOS. Two

ports are provided, allowing the array to be accessed simulta-

neously. Simultaneous access to a location triggers determin-

istic access control. For FullFlex72 these ports can operate

independently with 72-bit bus widths and each port can be

independently configured for two pipelined stages. Each port

can also be configured to operate in pipelined or flow-through

mode.

Advanced features include built-in deterministic access

control to manage address collisions during simultaneous

access to the same memory location, Variable Impedance

Matching (VIM) to improve data transmission by matching the

output driver impedance to the line impedance, and echo

clocks to improve data transfer.

To reduce the static power consumption, chip enables can be

used to power down the internal circuitry. The number of

cycles of latency before a change in CE0 or CE1 will enable

or disable the databus matches the number of cycles of read

latency selected for the device. In order for a valid write or read

to occur, both chip enable inputs on a port must be active.

Each port contains an optional burst counter on the input

address register. After externally loading the counter with the

initial address, the counter will increment the address inter-

nally.

Additional features of this device include a mask register and

a mirror register to control counter increments and

wrap-around. The counter-interrupt (CNTINT) flags notify the

host that the counter will reach maximum count value on the

next clock cycle. The host can read the burst-counter internal

address, mask register address, and busy address on the

address lines. The host can also load the counter with the

address stored in the mirror register by utilizing the retransmit

functionality. Mailbox interrupt flags can be used for message

passing, and JTAG boundary scan and asynchronous Master

Reset (MRST) are also available. The logic block diagram in

Figure 1

displays these features.

The FullFlex72 is offered in a 484-ball plastic BGA package.

The FullFlex36 and FullFlex18 are offered in both 484-ball and

256-ball fine pitch BGA packages.

Cypress Semiconductor Corporation

Document #: 38-06082 Rev. *G

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised December 21, 2006

CYD18S18V18-167BBXC Related Products

	CYD18S18V18-167BBXC	CYD18S18V18-250BBXC	CYD18S18V18-200BBXI	CYD18S18V18-200BBXC	CYD18S18V18-167BBXI
Description	sram 18m sync dual port 1mx18 90nm sdr com	sram 18m sync dual port 1mx18 90nm sdr com	sram 18m sync dual port 1mx18 90nm sdr ind	sram 18m sync dual port 1mx18 90nm sdr com	sram 18m sync dual port 1mx18 90nm sdr ind
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to
Maker	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor
Parts packaging code	BGA	BGA	BGA	BGA	BGA
package instruction	LBGA, BGA256,16X16,40	19 X 19 MM, 1.70 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-256	LBGA, BGA256,16X16,40	LBGA, BGA256,16X16,40	LBGA, BGA256,16X16,40
Contacts	256	256	256	256	256
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	11 ns	7.2 ns	9 ns	9 ns	11 ns
Other features	PIPELINED OR FLOW-THROUGH ARCHITECTURE, IT CAN ALSO OPERATES AT 1.8V	PIPELINED OR FLOW-THROUGH ARCHITECTURE, IT CAN ALSO OPERATES AT 1.8V	PIPELINED OR FLOW-THROUGH ARCHITECTURE, IT CAN ALSO OPERATES AT 1.8V	PIPELINED OR FLOW-THROUGH ARCHITECTURE, IT CAN ALSO OPERATES AT 1.8V	PIPELINED OR FLOW-THROUGH ARCHITECTURE, IT CAN ALSO OPERATES AT 1.8V
Maximum clock frequency (fCLK)	167 MHz	250 MHz	200 MHz	200 MHz	167 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	S-PBGA-B256	S-PBGA-B256	S-PBGA-B256	S-PBGA-B256	S-PBGA-B256
JESD-609 code	e1	e1	e1	e1	e1
length	19 mm	19 mm	19 mm	19 mm	19 mm
memory density	18874368 bit	18874368 bit	18874368 bit	18874368 bit	18874368 bit
Memory IC Type	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM
memory width	18	18	18	18	18
Humidity sensitivity level	3	3	3	3	3
Number of functions	1	1	1	1	1
Number of ports	2	2	2	2	2
Number of terminals	256	256	256	256	256
word count	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words
character code	1000000	1000000	1000000	1000000	1000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	85 °C	70 °C	85 °C
organize	1MX18	1MX18	1MX18	1MX18	1MX18
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LBGA	LBGA	LBGA	LBGA
Encapsulate equivalent code	BGA256,16X16,40	BGA256,16X16,40	BGA256,16X16,40	BGA256,16X16,40	BGA256,16X16,40
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	260	260	260	260	260
power supply	1.5/1.8 V	1.5/1.8 V	1.5/1.8 V	1.5/1.8 V	1.5/1.8 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.7 mm	1.7 mm	1.7 mm	1.7 mm	1.7 mm
Maximum standby current	0.3 A	0.3 A	0.35 A	0.3 A	0.35 A
Minimum standby current	1.4 V	1.4 V	1.4 V	1.4 V	1.4 V
Maximum slew rate	0.69 mA	0.88 mA	0.83 mA	0.77 mA	0.75 mA
Maximum supply voltage (Vsup)	1.58 V	1.58 V	1.58 V	1.58 V	1.58 V
Minimum supply voltage (Vsup)	1.42 V	1.42 V	1.42 V	1.42 V	1.42 V
Nominal supply voltage (Vsup)	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	20	20	20	20	20
width	19 mm	19 mm	19 mm	19 mm	19 mm
Base Number Matches	1	1	1	1	1

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