CYD04S72V18-167BBXI datasheet, PDF

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CYD04S72V18-167BBXI: Descriptionsram 4M sync dual port 64kx72 90nm ind; Categorystorage storage; File Size1MB，52 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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CYD04S72V18-167BBXI Overview

sram 4M sync dual port 64kx72 90nm ind

CYD04S72V18-167BBXI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-484
Contacts	484
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	4 ns
JESD-30 code	S-PBGA-B484
JESD-609 code	e1
length	23 mm
memory density	4718592 bit
Memory IC Type	DUAL-PORT SRAM
memory width	72
Humidity sensitivity level	3
Number of functions	1
Number of terminals	484
word count	65536 words
character code	64000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	64KX72
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	2.16 mm
Maximum supply voltage (Vsup)	1.58 V
Minimum supply voltage (Vsup)	1.42 V
Nominal supply voltage (Vsup)	1.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	23 mm
Base Number Matches	1

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FullFlex

FullFlex™ Synchronous SDR Dual Port SRAM

Features

■

Functional Description

The FullFlex™ dual port SRAM families consist of 2 Mbit, 4 Mbit,

9 Mbit, 18 Mbit, and 36 Mbit synchronous, true dual port static

RAMs that are high speed, low power 1.8V or 1.5V CMOS. Two

ports are provided, enabling simultaneous access to the array.

Simultaneous access to a location triggers deterministic access

control. For FullFlex72 these ports operate independently with

72-bit bus widths and each port is independently configured for

two pipelined stages. Each port is also configured to operate in

pipelined or flow through mode.

The advanced features include the following:

■

True dual port memory enables simultaneous access to the

shared array from each port

Synchronous pipelined operation with Single Data Rate (SDR)

operation on each port

❐

SDR interface at 200 MHz

❐

Up to 28.8 Gb/s bandwidth (200 MHz x 72 bit x 2 ports)

Selectable pipelined or flow-through mode

1.5V or 1.8V core power supply

Commercial and Industrial temperature

IEEE 1149.1 JTAG boundary scan

Available in 484-Ball PBGA (x72) and 256-Ball FBGA (x36 and

x18) packages

FullFlex72 family

❐

36 Mbit: 512K x 72 (CYD36S72V18)

❐

18 Mbit: 256K x 72 (CYD18S72V18)

❐

9 Mbit: 128K x 72 (CYD09S72V18)

❐

4 Mbit: 64K x 72 (CYD04S72V18)

FullFlex36 family

❐

36 Mbit: 1M x 36 (CYD36S36V18)

❐

18 Mbit: 512K x 36 (CYD18S36V18)

❐

9 Mbit: 256K x 36 (CYD09S36V18)

❐

4 Mbit: 128K x 36 (CYD04S36V18)

❐

2 Mbit: 64K x 36 (CYD02S36V18)

FullFlex18 family

❐

36 Mbit: 2M x 18 (CYD36S18V18)

❐

18 Mbit: 1M x 18 (CYD18S18V18)

❐

9 Mbit: 512K x 18 (CYD09S18V18)

❐

4 Mbit: 256K x 18 (CYD04S18V18)

Built in deterministic access control to manage address colli-

sions

❐

Deterministic flag output upon collision detection

❐

Collision detection on back-to-back clock cycles

❐

First Busy Address readback

Advanced features for improved high speed data transfer and

flexibility

❐

Variable Impedance Matching (VIM)

❐

Echo clocks

❐

Selectable LVTTL (3.3V), Extended HSTL (1.4V–1.9V), 1.8V

LVCMOS, or 2.5V LVCMOS IO on each port

❐

Burst counters for sequential memory access

❐

Mailbox with interrupt flags for message passing

❐

Dual Chip Enables for easy depth expansion

■

Built in deterministic access control to manage address colli-

sions during simultaneous access to the same memory location

Variable Impedance Matching (VIM) to improve data trans-

mission by matching the output driver impedance to the line

impedance

Echo clocks to improve data transfer

■

To reduce the static power consumption, chip enables power

down the internal circuitry. The number of latency cycles before

a change in CE0 or CE1 enables or disables the databus

matches the number of cycles of read latency selected for the

device. For a valid write or read to occur, activate both chip

enable inputs on a port.

Each port contains an optional burst counter on the input address

address, the counter increments the address internally.

Additional device features include a mask register and a mirror

counter interrupt (CNTINT) flags notify the host that the counter

reaches maximum count value on the next clock cycle. The host

reads the burst counter internal address, mask register address,

and busy address on the address lines. The host also loads the

counter with the address stored in the mirror register by using the

retransmit functionality. Mailbox interrupt flags are used for

message passing, and JTAG boundary scan and asynchronous

Master Reset (MRST) are also available. The

Logic Block

Diagram

on page 2 shows these features.

The FullFlex72 is offered in a 484-Ball plastic BGA package. The

FullFlex36 and FullFlex18 are available in 256-Ball fine pitch

BGA package.

■

Cypress Semiconductor Corporation

Document Number: 38-06082 Rev. *H

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised May 15, 2008

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