CYD04S18V18-200BBXI datasheet, PDF

Datasheet> All Categories > storage> storage> CYD04S18V18-200BBXI

CYD04S18V18-200BBXI: Descriptionsram 4M sync dual port 256kx18 90nm ind; Categorystorage storage; File Size1MB，52 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

Download Datasheet Parametric View All

CYD04S18V18-200BBXI Overview

sram 4M sync dual port 256kx18 90nm ind

CYD04S18V18-200BBXI Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	17 X 17 MM, 1 MM PITCH, LEAD FREE, MO-192, FBGA-256
Contacts	256
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	9 ns
Other features	PIPELINED OR FLOW-THROUGH ARCHITECTURE, IT CAN ALSO OPERATES AT 1.8V
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
JESD-30 code	S-PBGA-B256
JESD-609 code	e1
length	17 mm
memory density	4718592 bit
Memory IC Type	DUAL-PORT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of ports	2
Number of terminals	256
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA256,16X16,40
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	1.5/1.8 V
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum standby current	0.17 A
Minimum standby current	1.4 V
Maximum slew rate	0.62 mA
Maximum supply voltage (Vsup)	1.58 V
Minimum supply voltage (Vsup)	1.42 V
Nominal supply voltage (Vsup)	1.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	17 mm
Base Number Matches	1

Preview

Download Datasheet

View All

FullFlex

FullFlex™ Synchronous SDR Dual Port SRAM

Features

■

Functional Description

The FullFlex™ dual port SRAM families consist of 2 Mbit, 4 Mbit,

9 Mbit, 18 Mbit, and 36 Mbit synchronous, true dual port static

RAMs that are high speed, low power 1.8V or 1.5V CMOS. Two

ports are provided, enabling simultaneous access to the array.

Simultaneous access to a location triggers deterministic access

control. For FullFlex72 these ports operate independently with

72-bit bus widths and each port is independently configured for

two pipelined stages. Each port is also configured to operate in

pipelined or flow through mode.

The advanced features include the following:

■

True dual port memory enables simultaneous access to the

shared array from each port

Synchronous pipelined operation with Single Data Rate (SDR)

operation on each port

❐

SDR interface at 200 MHz

❐

Up to 28.8 Gb/s bandwidth (200 MHz x 72 bit x 2 ports)

Selectable pipelined or flow-through mode

1.5V or 1.8V core power supply

Commercial and Industrial temperature

IEEE 1149.1 JTAG boundary scan

Available in 484-Ball PBGA (x72) and 256-Ball FBGA (x36 and

x18) packages

FullFlex72 family

❐

36 Mbit: 512K x 72 (CYD36S72V18)

❐

18 Mbit: 256K x 72 (CYD18S72V18)

❐

9 Mbit: 128K x 72 (CYD09S72V18)

❐

4 Mbit: 64K x 72 (CYD04S72V18)

FullFlex36 family

❐

36 Mbit: 1M x 36 (CYD36S36V18)

❐

18 Mbit: 512K x 36 (CYD18S36V18)

❐

9 Mbit: 256K x 36 (CYD09S36V18)

❐

4 Mbit: 128K x 36 (CYD04S36V18)

❐

2 Mbit: 64K x 36 (CYD02S36V18)

FullFlex18 family

❐

36 Mbit: 2M x 18 (CYD36S18V18)

❐

18 Mbit: 1M x 18 (CYD18S18V18)

❐

9 Mbit: 512K x 18 (CYD09S18V18)

❐

4 Mbit: 256K x 18 (CYD04S18V18)

Built in deterministic access control to manage address colli-

sions

❐

Deterministic flag output upon collision detection

❐

Collision detection on back-to-back clock cycles

❐

First Busy Address readback

Advanced features for improved high speed data transfer and

flexibility

❐

Variable Impedance Matching (VIM)

❐

Echo clocks

❐

Selectable LVTTL (3.3V), Extended HSTL (1.4V–1.9V), 1.8V

LVCMOS, or 2.5V LVCMOS IO on each port

❐

Burst counters for sequential memory access

❐

Mailbox with interrupt flags for message passing

❐

Dual Chip Enables for easy depth expansion

■

Built in deterministic access control to manage address colli-

sions during simultaneous access to the same memory location

Variable Impedance Matching (VIM) to improve data trans-

mission by matching the output driver impedance to the line

impedance

Echo clocks to improve data transfer

■

To reduce the static power consumption, chip enables power

down the internal circuitry. The number of latency cycles before

a change in CE0 or CE1 enables or disables the databus

matches the number of cycles of read latency selected for the

device. For a valid write or read to occur, activate both chip

enable inputs on a port.

Each port contains an optional burst counter on the input address

address, the counter increments the address internally.

Additional device features include a mask register and a mirror

counter interrupt (CNTINT) flags notify the host that the counter

reaches maximum count value on the next clock cycle. The host

reads the burst counter internal address, mask register address,

and busy address on the address lines. The host also loads the

counter with the address stored in the mirror register by using the

retransmit functionality. Mailbox interrupt flags are used for

message passing, and JTAG boundary scan and asynchronous

Master Reset (MRST) are also available. The

Logic Block

Diagram

on page 2 shows these features.

The FullFlex72 is offered in a 484-Ball plastic BGA package. The

FullFlex36 and FullFlex18 are available in 256-Ball fine pitch

BGA package.

■

Cypress Semiconductor Corporation

Document Number: 38-06082 Rev. *H

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised May 15, 2008

[+] Feedback

Recommended Resources

Unidirectional thyristor AC voltage regulating circuit

555 RF driver audio oscillator circuit diagram

TA7282AP audio IC circuit diagram

Forward/reverse circuit composed of power op amp

450Hz audio signal generator circuit

Solar battery charger circuit

ISP download line + schematic diagram: ISP download line + schematic diagram can be used by friends who study microcontrollers!...; liushuimin MCU

[Ask] How to handle multiple interrupts in Keil more reasonably and avoid exceptions?: For example: I use a circular queue to store and send messages. The queue uses an array of fixed length, where the length of the array must be longer than each message. There are 8 arrays in the queue...; panyi1012 Embedded System

Transistor series voltage regulator circuit: Friends, can you recommend a few transistor series voltage regulator circuits? The photo above is just one of them. I have been busy with this recently and have not found a suitable one!...; zhangdaoyu Analog electronics

Read Ren Zhe's study notes on "Principles and Applications of Embedded Real-Time Operating System Uc/os-ii": I have been studying Ren Zhe's "Principles and Applications of Embedded Real-time Operating System UCOS-II" for a week and have read two chapters. I would like to summarize some of my gains, problems ...; SUNISMYSELF stm32/stm8

The guitar I exchanged for gold coins has arrived: The guitar I bought with my gold coins has arrived! Unfortunately, I still can't play it well, I'm still learning......; mumuxiangzi Talking

Register for the 2018 Munich Shanghai Electronics Show and get a Starbucks coffee coupon! Everyone has a share...: [font=微软雅黑][size=4][color=#696969][i]The Munich Shanghai Electronics Show, which always brings surprises to everyone, will be held in March! [/i][/color][/size][/font] [font=微软雅黑][size=4][color=#69696...; EEWORLD社区 Integrated technical exchanges

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components