D27C256 datasheet, PDF - EEWORLD Datasheet

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D27C256: Description256 Kilobit (32,768 x 8-bit) cmos eprom; File Size91KB，12 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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D27C256 Overview

256 Kilobit (32,768 x 8-bit) cmos eprom

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Am27C256

256 Kilobit (32,768 x 8-Bit) CMOS EPROM

DISTINCTIVE CHARACTERISTICS

Fast access time

—

55 ns

Low power consumption

—

µA

typical CMOS standby current

JEDEC-approved pinout

Single +5 V power supply

±10%

power supply tolerance available

100% Flashrite programming

— Typical programming time of 4 seconds

Advanced

Micro

Devices

Latch-up protected to 100 mA from –1 V to

+ 1 V

High noise immunity

Versatile features for simple interfacing

— Both CMOS and TTL input/output

compatibility

— Two line control functions

Standard 28-pin DIP, PDIP, 32-pin TSOP and

PLCC packages

GENERAL DESCRIPTION

The Am27C256 is a 256K-bit ultraviolet erasable pro-

grammable read-only memory. It is organized as 32K

words by 8 bits per word, operates from a single +5 V

supply, has a static standby mode, and features fast sin-

gle address location programming. Products are avail-

able in windowed ceramic DIP packages as well as plas-

tic one time programmable (OTP) PDIP, TSOP, and

PLCC packages.

Typically, any byte can be accessed in less than 55 ns,

allowing operation with high-performance microproces-

sors without any WAIT states. The Am27C256 offers

separate Output Enable (OE) and Chip Enable (CE)

controls, thus eliminating bus contention in a multiple

bus microprocessor system.

AMD’s CMOS process technology provides high speed,

low power, and high noise immunity. Typical power con-

sumption is only 80 mW in active mode, and 100

µW

standby mode.

All signals are TTL levels, including programming sig-

nals. Bit locations may be programmed singly, in blocks,

or at random. The Am27C256 supports AMD’s Flashrite

programming algorithm (100

µs

pulses) resulting in typi-

cal programming time of 4 seconds.

BLOCK DIAGRAM

Data Outputs

DQ0–DQ7

Output Enable

Chip Enable

and

Prog Logic

Decoder

Output

Buffers

Gating

A0–A14

Address

Inputs

Decoder

262,144

Bit Cell

Matrix

08007H-1

2-32

Publication#

08007

Rev.

Issue Date:

May 1995

Amendment

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