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DPS2ME16MKJ3-25C

Description
SRAM Module, 2MX16, 25ns, CMOS
Categorystorage    storage   
File Size497KB,8 Pages
ManufacturerB&B Electronics Manufacturing Company
Download Datasheet Parametric View All

DPS2ME16MKJ3-25C Overview

SRAM Module, 2MX16, 25ns, CMOS

DPS2ME16MKJ3-25C Parametric

Parameter NameAttribute value
MakerB&B Electronics Manufacturing Company
package instruction,
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time25 ns
Spare memory width8
JESD-30 codeR-XQMA-J52
memory density33554432 bit
Memory IC TypeSRAM MODULE
memory width16
Number of functions1
Number of terminals52
word count2097152 words
character code2000000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize2MX16
Package body materialUNSPECIFIED
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formJ BEND
Terminal locationQUAD
Base Number Matches1
2Mx16, 20 - 45ns, STACK
30A129-28
B
32 Megabit High Speed CMOS SRAM
DESCRIPTION:
The DPS2ME16MKn3 High Speed SRAM ‘’STACK’’ modules are a
revolutionary new memory subsystem using Dense-Pac
Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC).
Available in straight leaded, ‘’J’’ leaded or gullwing leaded
packages. The module packs 32-Megabits of low-power CMOS
static RAM in an area as small as 0.549 in
2
, while maintaining a
total height as low as 0.545 inches.
The DPS2ME16MKn3 STACK modules contain eight individual
512K x 8 SRAMs, each packaged in a hermetically sealed SLCC,
making the modules suitable for commercial, industrial and military
applications.
By using SLCCs, the ‘’Stack’’ family of modules offer a higher board
density of memory than available with conventional through-hole,
surface mount or hybrid techniques.
SLCC Stack
DPS2ME16MKn3
Straight
Leaded
Stack
FEATURES:
Organizations Available:
2 Meg x 16 or 4 Meg x 8
Access Times:
20*, 25, 30, 35, 45ns
Fully Static Operation - No clock or refresh required
Single +5V Power Supply,
±
10% Tolerance
TTL Compatible
Common Data Inputs and Outputs
Low Data Retention Voltage:
2.0V min.
Packages Available:
SLCC Stack
Straight Leaded Stack
‘’J’’ Leaded Stack
Gullwing Leaded Stack
‘’J’’ Leaded
Stack
*
Commercial and Industrial Grade only.
Gullwing
Leaded
Stack
FUNCTIONAL BLOCK DIAGRAM
PIN NAMES
A0 - A18
I/O0 - I/O15
CE0 - CE3
WE0, WE1
OE0, OE1
V
DD
V
SS
N.C.
30A129-28
REV. B
This document contains information on a product presently under
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right
to change products or specifications herein without prior notice.
Address Inputs
Data Input/Output
Low Chip Enables
Write Enables
Output Enables
Power (+5V)
Ground
No Connect
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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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