INTEGRATED CIRCUITS
PDI1284P11
3.3V Parallel interface transceiver/buffer
Product specification
Supersedes data of 1997 Sep 15
1999 Sep 17
Philips
Semiconductors
Philips Semiconductors
Product specification
3.3V Parallel interface transceiver/buffer
PDI1284P11
FEATURES
•
Asynchronous operation
•
8-Bit transceivers
•
6 additional buffer/driver lines peripheral to cable
•
5 additional control lines from cable
•
5V tolerant
•
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The PDI1284P11 parallel interface chip is designed to provide an
asynchronous, 8-bit, bi-directional, parallel interface for personal
computers. The part includes all 19 signal lines defined by the
IEEE1284 interface specification for Byte, Nibble, EPP, and ECP
modes. The part is designed for hosts or peripherals operating at
3.3V to interface 3.3V or 5.0V devices.
The 8 transceiver pairs (A/B 1-8) allow data transmission from the A
bus to the B bus, or from the B bus to the A bus, depending on the
state of the direction pin DIR.
The B bus and the Y9-Y13 lines have either totem pole or resistor
pull up outputs, depending on the state of the high drive enable pin
HD. The A bus has only totem pole style outputs. All inputs are TTL
compatible with at least 400mV of input hysteresis at V
CC
= 3.3V.
•
Latch up protection exceeds 500 mA per JEDEC Std 19
•
Input Hysteresis
•
Low Noise Operation
•
IEEE 1284 Compliant Level 1 & 2
•
Overvoltage Protection on B/Y side for OFF-state
•
A side 3-State option
•
B side active or resistive pull up option
•
Cable side V
CC
for 5V or 3V operation
QUICK REFERENCE DATA
SYMBOL
R
D
R
PU
SR
I
CC
V
HYS
t
PLH
/t
PHL
A –B/Y
PARAMETER
B/Y Side output resistance
B/Y side pull up resistance
B/Y Side slew rate
Total static current
Input hysteresis
Propagation delay
to the B/Y side outputs
CONDITIONS
T
amb
= 25°C; GND = 0V
V
CC
= 3.3V; V
O
= 1.65V
±0.2V
(See Figure 2)
V
CC
= 3.3V; Outputs, resistive pull up
R
L
= 62Ω; C
L
= 50pF (See Waveform 4)
V
I
= V
CC
/GND; I
O
= 0
V
CC
= 3.3V
V
CC
= 3.3V
TYPICAL
45
1.4K
0.2
5
0.47
12.5/13.9
UNIT
Ω
Ω
V/ns
µA
V
ns
ORDERING INFORMATION
PACKAGES
48-pin plastic SSOP Type II
48-pin plastic TSSOP Type II
TEMPERATURE RANGE
0°C to +70°C
0°C to +70°C
ORDER CODE
PDI1284P11 DL
PDI1284P11 DGG
DRAWING NUMBER
SOT370-1
SOT362-1
1999 Sep 17
2
853–2036 22356
Philips Semiconductors
Product specification
3.3V Parallel interface transceiver/buffer
PDI1284P11
PIN CONFIGURATION
HD
A9
A10
A11
A12
A13
V
CC
A1
A2
GND
A3
A4
A5
A6
GND
A7
A8
V
CC
PLHI
A14
A15
A16
A17
HLHO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DIR
Y9
Y10
Y11
Y12
Y13
V
CCB
B1
B2
GND
B3
B4
B5
B6
OEA
B7
B8
V
CCB
PLHO
PIN DESCRIPTION
PIN NUMBER
8, 9, 11, 12, 13,
14, 16, 17
41, 40, 38, 37,
36, 35, 33, 32
2, 3, 4, 5, 6
47, 46, 45, 44, 43
29, 28, 27, 26
20, 21, 22, 23
1
48
19
30
25
24
10, 15, 39
C14
SYMBOL
A1 - A8
B1 - B8
A9 - A13
Y9 - Y3
C14 - C17
A19 - A17
HD
DIR
PLHI
PLHO
HLHI
HLHO
GND
V
CC
V
CCB
OEA
FUNCTION
Data inputs/outputs
IEEE 1284 Std.
outputs/inputs
Data inputs
IEEE 1284 Std. outputs
Control inputs (cable)
Control outputs
(peripheral)
B/Y–side high drive
enable/disable
Direction selection
A to B / B to A
Peripheral logic high input
(peripheral)
Peripheral logic high
output (cable)
Host logic high input
(cable)
Host logic high output
(cable)
Ground (0V)
Positive supply voltage
Cable side power supply
voltage 3V/5V
A side output enable
7, 18
C15
C16
C17
HLHI
31, 42
34
SV00496
1999 Sep 17
3
Philips Semiconductors
Product specification
3.3V Parallel interface transceiver/buffer
PDI1284P11
LOGIC SYMBOL
HD
HD
HD
HD
HD
HD
HD
CNTL
DIR
OEA
Y9
Y10
Y11
Y12
Y13
FUNCTION TABLE
DIR
X
OEA
X
X
X
X
X
X
X
X
L
H
H
HD
X
X
L
H
L
H
L
H
X
X
X
B1-8
INPUTS
C14-17
HLHI
A9-13
A9-13
PLHI
PLHI
A1-8
A1-8
B1-8
OUTPUTS
A14-17
HLHO
Y9-13
Y9-13
PLHO
PLHO
B1-8
B1-8
A1-8
A1-8
OUTPUT
TYPES
t
P
t
P
r
P
t
P
O.C.
t
P
r
P
t
P
t
P
Z*
r
P*
A9
A10
A11
A12
A13
X
X
X
X
X
H
H
L
L
L
A =
B =
C =
Y =
X =
Z =
O.C.=
t
P
=
r
P
=
HD
A1
CNTL
HD
A2
CNTL
HD
A3
CNTL
A4
CNTL
A5
CNTL
A6
CNTL
HD
A7
CNTL
A8
CNTL
PLHI
A14
A15
A16
A17
HLHO
PERIPHERAL
SIDE
HD
PLHO
C14
C15
C16
C17
HLHI
CABLE
SIDE
HD
B8
B7
HD
B6
HD
B5
HD
B4
B3
B2
B1
*
Side driving internal IC
Side driving external cable (bidirectional)
Side receiving control signals from internal cable
Side driving external cable (unidirectional)
Don’t care – control signals in
High Z or 3-State
Open collector
Totem pole output
Resistive pull up: 1.4kΩ (nominal) on B/Y/C cable side and
V
CC
. However, while a B/Y side output is Low as driven by a
Low signal on the A side, that particular B/Y side resistor is
switched out to stop current drain from V
CC
through it.
When DIR = L and OEA = H, the output signal is isolated
from the input signal. B1 – 8 signals maintain an r
P
= 1.4kΩ
on the input for this mode.
SV00136
PINS WITH PULL UP RESISTORS TO LOAD CABLE
PINS
47, 46, 45, 44, 43
41, 40, 38, 37, 36,
35, 33, 32
29, 28, 27, 26
SYMBOL
Y9 – Y13
B1 – B8
C14 – C17
FUNCTION
Output cable drivers
Output cable drivers
External cables control signal
input
1999 Sep 17
4
Philips Semiconductors
Product specification
3.3V Parallel interface transceiver/buffer
PDI1284P11
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER
ESD Immunity, per Mil Std 883C method 3015
V
CC
V
CCB
I
IK
I
OK
V
IN
V
OUT
B/Y
V
OUT
B/Y
V
OUT
A
I
O
T
stg
I
CC
/I
GND
DC supply voltage
DC cable supply voltage
DC input diode current
DC output diode current
DC input voltage
3
DC output voltage on B/Y side
3
Transient output voltage on B/Y side
4
DC output voltage on A side
DC output current
Storage temperature range
Continuous current through V
CC
or GND
Outputs in High or Low state
40ns transient
V
I
< 0
V
O
< 0
CONDITIONS
RATING
"1
–0.5 to +4.6
–0.5 to +6.5
±20
±50
–0.5 to +5.5
–0.5 to +5.5
–2 to +7
–0.5 to V
CC
+0.5
±50
–60 to +150
±200
UNIT
kV
V
V
mA
mA
V
V
V
V
mA
°C
mA
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
4. V
OUT
B/Y (tr) guarantees only that this part will not be damaged by reflections in application so long as the voltage levels remain in the
specified range.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
CCB
V
IH
V
IL
V
OUT
B/Y
V
OUT
A
I
OH
I
OL
T
amb
DC supply voltage
DC cable supply voltage
High level Input voltage
Low level input voltage
B/Y output voltage
A side output voltage
B/Y side output current High
B/Y side output current Low
Operating free-air temperature range
0
–0.5
0
PARAMETER
MIN
3.0
3.0
2.0
0.8
5.5
V
CC
–14
14
+70
MAX
3.6
5.5
UNIT
V
V
V
V
V
V
mA
mA
°C
1999 Sep 17
5
京公网安备 11010802033920号
EEWORLD
