D85C224-80 datasheet, PDF - EEWORLD Datasheet

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D85C224-80: Descriptionfast registered speed tsu,tso 8-macrocell; CategoryProgrammable logic devices Programmable logic; File Size943KB，18 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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D85C224-80 Overview

fast registered speed tsu,tso 8-macrocell

D85C224-80 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
Parts packaging code	DIP
package instruction	0.300 INCH, CERDIP-24
Contacts	24
Reach Compliance Code	compliant
Is Samacsys	N
Other features	PAL WITH MACROCELLS; 8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Architecture	PAL-TYPE
maximum clock frequency	80 MHz
JESD-30 code	R-GDIP-T24
JESD-609 code	e0
length	32.07 mm
Dedicated input times	13
Number of I/O lines	8
Number of entries	22
Output times	8
Number of product terms	72
Number of terminals	24
Maximum operating temperature	70 °C
Minimum operating temperature
organize	13 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Encapsulate equivalent code	DIP24,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	UV PLD
propagation delay	12 ns
Certification status	Not Qualified
Maximum seat height	5.72 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
Base Number Matches	1

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D85C224-80 Related Products

	D85C224-80	D85C224-66
Description	fast registered speed tsu,tso 8-macrocell	fast registered speed tsu,tso 8-macrocell
Is it Rohs certified?	incompatible	incompatible
Maker	Intel	Intel
Parts packaging code	DIP	DIP
package instruction	0.300 INCH, CERDIP-24	0.300 INCH, CERDIP-24
Contacts	24	24
Reach Compliance Code	compliant	compliant
Is Samacsys	N	N
Other features	PAL WITH MACROCELLS; 8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	PAL WITH MACROCELLS; 8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Architecture	PAL-TYPE	PAL-TYPE
maximum clock frequency	80 MHz	66 MHz
JESD-30 code	R-GDIP-T24	R-GDIP-T24
JESD-609 code	e0	e0
length	32.07 mm	32.07 mm
Dedicated input times	13	13
Number of I/O lines	8	8
Number of entries	22	22
Output times	8	8
Number of product terms	72	72
Number of terminals	24	24
Maximum operating temperature	70 °C	70 °C
organize	13 DEDICATED INPUTS, 8 I/O	13 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL	MACROCELL
Package body material	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED
encapsulated code	DIP	DIP
Encapsulate equivalent code	DIP24,.3	DIP24,.3
Package shape	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	5 V
Programmable logic type	UV PLD	UV PLD
propagation delay	12 ns	12 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	5.72 mm	5.72 mm
Maximum supply voltage	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V
surface mount	NO	NO
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	7.62 mm	7.62 mm
Base Number Matches	1	1

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