DAC712 is a complete 16-bit resolution D/A converter
with 16 bits of monotonicity over temperature.
DAC712 has a precision +10V temperature compen-
sated voltage reference,
±10V
output amplifier and
16-bit port bus interface.
The digital interface is fast, 60ns minimum write pulse
width, is double-buffered and has a CLEAR function
that resets the analog output to bipolar zero.
GAIN and OFFSET adjustment inputs are arranged so
that they can be easily trimmed by external D/A
converters as well as by potentiometers.
DAC712 is available in two linearity error perfor-
mance grades:
±4LSB
and
±2LSB
and three differen-
tial linearity grades:
±4LSB, ±2LSB,
and
±1LSB.
The
DAC712 is specified at power supply voltages of
±12V
and
±15V.
DAC712 is packaged in a 28-pin 0.3" wide plastic DIP
and in a 28-lead wide-body plastic SOIC. The
DAC712P, U, PB, UB, are specified over the –40°C to
+85°C temperature range and the DAC712PK, UK,
PL, UL are specified over the 0°C to +70°C range.
DB0
DB15
A
1
A
0
WR
CLR
Input Latch
16
D/A Latch
16
Reference
Circuit
16-Bit D/A Converter
V
OUT
Gain Adjust
V
REF OUT
+10V
Bipolar Offset Adjust
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
NOTES: (1) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (2) FSR means Full Scale Range. For example, for a
±10V
output, FSR = 20V. (3) Errors externally adjustable to zero. (4) Maximum represents the 3σ limit. Not 100% tested for this parameter. (5) For the worst case code changes:
FFFF
HEX
to 0000
HEX
and 0000
HEX
to FFFF
HEX
. These are Binary Two’s Complement (BTC) codes. (6) Typical supply voltages times maximum currents.
®
DAC712PB, UB
MAX
MIN
TYP
T
T
T
T
T
T
T
T
V
V
µA
µA
MAX
UNITS
Bits
MIN
TYP
16
Binary Two’s Complement
+2.0
0
+V
CC
– 1.4
+0.8
±10
±10
±4
±8
±4
±8
13
±0.1
±0.2
±0.1
±20
±0.2
±40
±0.003
±30
14
±2
±4
±2
±4
±0.1
±0.15
T
T
±0.15
±30
T
T
LSB
LSB
LSB
LSB
Bits
%
%
% FSR
(2)
mV
% FSR
mV
% FSR/% V
CC
ppm FSR/% V
CC
6
4
10
0.005
0.03
3.0
87
2
15
120
T
T
T
T
T
T
T
T
T
T
10
µs
µs
V/µs
%
%
%
dB
nV-s
nV-s
nV/√Hz
±10
±5
0.1
Indefinite
+9.975
+9.960
2
Indefinite
+11.4
–11.4
+15
–15
13
22
525
+16.5
–16.5
15
25
600
+10.000
1
+10.025
+10.040
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
V
mA
Ω
V
V
Ω
mA
V
V
mA
mA
mW
–40
–60
75
75
+85
+150
T
T
T
T
T
T
°C
°C
°C/W
°C/W
DAC712
2
SPECIFICATIONS
ELECTRICAL
At T
A
= +25°C, +V
CC
= +12V and +15V, –V
CC
= –12V and –15V, unless otherwise noted.
DAC712PK, UK
PARAMETER
INPUT
RESOLUTION
DIGITAL INPUTS
Input Code
Logic Levels
(1)
V
IH
V
IL
I
IH
(V
I
= +2.7V)
I
IL
(V
I
= +0.4V)
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error
T
MIN
to T
MAX
Differential Linearity Error
T
MIN
to T
MAX
Monotonicity Over Temp
Gain Error
(3)
T
MIN
to T
MAX
Bipolar Zero Error
(3)
T
MIN
to T
MAX
Power Supply Sensitivity of Full Scale
DYNAMIC PERFORMANCE
Settling Time (to
±0.003%FSR,
5kΩ || 500pF Load)
(4)
20V Output Step
1LSB Output Step
(5)
Output Slew Rate
Total Harmonic Distortion + Noise
0dB, 1001Hz, f
S
= 100kHz
–20dB, 1001Hz, f
S
= 100kHz
–60dB, 1001Hz, f
S
= 100kHz
SINAD
1001Hz, f
S
= 100kHz
Digital Feedthrough
(5)
Digital-to-Analog Glitch Impulse
(5)
Output Noise Voltage (includes reference)
ANALOG OUTPUT
Output Voltage Range
+V
CC
, –V
CC
=
±11.4V
Output Current
Output Impedance
Short Circuit to ACOM, Duration
REFERENCE VOLTAGE
Voltage
T
MIN
to T
MAX
Output Resistance
Source Current
Short Circuit to ACOM, Duration
POWER SUPPLY REQUIREMENTS
Voltage: +V
CC
–V
CC
Current (No Load,
±15V
Supplies)
+V
CC
–V
CC
Power Dissipation
(6)
TEMPERATURE RANGES
Specification
All Grades
Storage
Thermal Coefficient,
θ
JA
DIP Package
SOIC Package
T
Same specification as grade to the left.
NOTES: (1) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (2) FSR means Full Scale Range. For example, for a
±10V
output, FSR = 20V. (3) Errors externally adjustable to zero. (4) Maximum represents the 3σ limit. Not 100% tested for this parameter. (5) For the worst case code changes:
FFFF
HEX
to 0000
HEX
and 0000
HEX
to FFFF
HEX
. These are Binary Two’s Complement (BTC) codes. (6) Typical supply voltages times maximum currents.
®
DAC712PL, UL
MAX
MIN
TYP
MAX
UNITS
MIN
TYP
16
Binary Two’s Complement
+2.0
0
+V
CC
– 1.4
+0.8
±10
±10
T
T
T
T
T
T
T
T
Bits
V
V
µA
µA
±2
±2
±2
±2
15
±0.1
±0.15
±0.1
±20
±0.15
±30
±0.003
±30
16
±2
±2
±1
±1
T
±0.02
T
T
±0.15
T
T
T
LSB
LSB
LSB
LSB
Bits
%
%
% FSR
(2)
mV
% FSR
mV
%FSR/% V
CC
ppm FSR/% V
CC
6
4
10
0.005
0.03
3.0
87
2
15
120
10
T
T
T
T
T
T
T
T
T
T
10
µs
µs
V/µs
%
%
%
dB
nV–s
nV–s
nV/√Hz
±10
±5
0.1
Indefinite
+9.975
+9.960
2
Indefinite
+11.4
–11.4
+15
–15
13
22
525
+16.5
–16.5
15
25
600
+10.000
1
+10.025
+10.040
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
V
mA
Ω
V
V
Ω
mA
V
V
mA
mA
mW
0
–60
75
75
+70
+150
T
T
T
T
T
T
°C
°C
°C/W
°C/W
3
DAC712
ABSOLUTE MAXIMUM RATINGS
+V
CC
to COMMON ...................................................................... 0V, +17V
–V
CC
to COMMON ...................................................................... 0V, –17V
Digital Inputs to COMMON .......................................... –1V to +V
CC
–0.7V
External Voltage Applied to BPO and Range Resistors .....................
±V
CC
V
REF OUT
...................................................... Indefinite Short to COMMON
V
OUT
............................................................ Indefinite Short to COMMON
Power Dissipation .......................................................................... 750mW
Storage Temperature ...................................................... –60°C to +150°C
Lead Temperature (soldering, 10s) ................................................ +300°C
NOTE: Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
TIMING DIAGRAM
t
AW
A
0
, A
1
t
AH
t
DW
D0-D15
t
DH
WR
t
WP
PACKAGE INFORMATION
PRODUCT
DAC712P
DAC712U
DAC712PB
DAC712UB
DAC712PK
DAC712UK
DAC712PL
DAC712UL
PACKAGE
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
PACKAGE DRAWING
NUMBER
(1)
246
217
246
217
246
217
246
217
TIMING SPECIFICATIONS
T
A
= –40°C to +85°C, +V
CC
= +12V or +15V, –V
CC
= –12V or –15V.
SYMBOL
t
DW
t
AW
t
AH
t
DH
t
WP(1)
t
CP
PARAMETER
Data Valid to End of WR
A
0
, A
1
Valid to End of WR
A
0
, A
1
Hold after End of WR
Data Hold after end of WR
Write Pulse Width
CLEAR Pulse Width
MIN
50
50
10
10
50
200
MAX
UNITS
ns
ns
ns
ns
ns
ns
NOTES: (1) For single-buffered operation, t
WP
is 80ns min. Refer to page 10.
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
TRUTH TABLE
ORDERING INFORMATION
TEMPERATURE
RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
LINEARITY
ERROR MAX
at +25
°
C
±4LSB
±4LSB
±2LSB
±2LSB
±2LSB
±2LSB
±2LSB
±2LSB
DIFFERENTIAL
LINEARITY ERROR
MAX at +25
°
C
±4LSB
±4LSB
±2LSB
±2LSB
±2LSB
±2LSB
±1LSB
±1LSB
A
0
0
1
1
0
X
X
A
1
1
0
1
0
X
X
WR
1
→
0
→
1
1
→
0
→
1
1
→
0
→
1
0
1
X
CLR
1
1
1
1
1
0
DESCRIPTION
Load Input Latch
Load D/A Latch
No Change
Latches Transparent
No Change
Reset D/A Latch
PRODUCT
DAC712P
DAC712U
DAC712PB
DAC712UB
DAC712PK
DAC712UK
DAC712PL
DAC712UL
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-Brown
Corporation recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published speci-
fications.
®
DAC712
4
PIN CONFIGURATION
PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
LABEL
DCOM
ACOM
V
OUT
Off Adj
V
REF OUT
Gain Adj
+V
CC
–V
CC
CLR
WR
A
1
A
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
Power Supply return for digital currents.
Analog Supply Return.
±10V
D/A Output.
Offset Adjust (Bipolar).
Voltage Reference Output.
Gain Adjust.
+12V to +15V Supply.
–12V to –15V Supply.
CLEAR. Sets D/A output to BIPOLAR ZERO
(Active Low).
Write (Active Low).
Enable for D/A latch (Active Low).
Enable for Input latch (Active Low).
Data Bit 15 (Most Significant Bit).
Data Bit 14.
Data Bit 13.
Data Bit 12.
Data Bit 11.
Data Bit 10.
Data Bit 9.
Data Bit 8.
Data Bit 7.
Data Bit 6.
Data Bit 5.
Data Bit 4.
Data Bit 3.
Data Bit 2.
Data Bit 1.
Data Bit 0 (Least Significant Bit).
DCOM
ACOM
V
OUT
Offset Adjust
V
REF OUT
Gain Adjust
+V
CC
–V
CC
CLR
WR
A
1
A
0
D15 MSB
D14
1
2
3
4
5
6
7
DAC712
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LSB D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
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Embedded System
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