parallel interface that is double buffered, and an asyn-
chronous clear function which immediately sets the
output voltage to one-half of full-scale.
The output voltage range is 0 to +10V while operating
from
±12V
or
±15V
supplies. The gain and bipolar
offset adjustments are designed so that they can be set
via external potentiometers or external D/A converters.
The output amplifier is protected against short circuit to
ground.
The 28-pin DAC715 is available in a 0.3" plastic DIP
and wide-body plastic SOIC package. The DAC715P,
U, PB, and UB are specified over the –40°C to +85°C
temperature range while the DAC715PK, UK, PL, and
UL are specified over the 0°C to +70°C range.
D0
D15
A
1
A
0
WR
CLR
Input Latch
16
D/A Latch
16
Reference
Circuit
16-Bit D/A Converter
V
OUT
Gain Adjust
V
REF OUT
+10V
Offset Adjust
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
and after a 10-minute warm-up, unless otherwise noted.
DAC715P, U
PARAMETER
INPUT
RESOLUTION
DIGITAL INPUTS
Input Code
Logic Levels
(1)
: V
IH
V
IL
I
IH
(V
I
= +2.7V)
I
IL
(V
I
= +0.4V)
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error
T
MIN
to T
MAX
Differential Linearity Error
T
MIN
to T
MAX
Monotonicity Over Temp
Gain Error
(3)
T
MIN
to T
MAX
Offset Error
(3)
T
MIN
to T
MAX
Power Supply Sensitivity Of Full Scale
DYNAMIC PERFORMANCE
Settling Time (to
±0.003%FSR,
5kΩ ll 500pF Load)
(4)
10V Output Step
1 LSB Output Step
(5)
Output Slew Rate
Total Harmonic Distortion + Noise
0dB, 1001Hz, f
S
= 100kHz
–20dB, 1001Hz, f
S
= 100kHz
–60dB, 1001Hz, f
S
= 100kHz
SINAD
1001Hz, f
S
= 100kHz
Digital Feedthrough
(5)
Digital-to-Analog Glitch Impulse
(5)
Output Noise Voltage
(includes Reference)
ANALOG OUTPUT
Output Voltage Range
+V
CC
, –V
CC
=
±11.4V
Output Current
Output Impedance
Short Circuit to ACOM
Duration
REFERENCE VOLTAGE
Voltage
T
MIN
to T
MAX
Output Resistance
Source Current
Short Circuit to ACOM, Duration
POWER SUPPLY REQUIREMENTS
Voltage: +V
CC
–V
CC
Current (no load,
±15V
Supplies)
+V
CC
–V
CC
Power Dissipation
TEMPERATURE RANGE
Specification All Grades
Storage
Thermal Resistance
θ
JA
DIP Package
SOIC Package
–40
–60
75
75
+85
+150
T
T
T
T
T
T
0
T
T
T
+70
T
T
T
T
T
T
T
±4
±8
±4
±8
13
±0.1
±0.2
±0.1
±0.2
±0.003
±30
14
±2
±4
±2
±4
±0.1
±0.15
T
T
T
T
15
T
T
T
T
T
T
±2
±2
±2
±2
16
T
T
T
T
T
T
±2
±2
±1
±1
LSB
LSB
LSB
LSB
Bits
%
%
% FSR
(2)
% FSR
% FSR/%V
CC
PPM FSR/%V
CC
16
Binary Two’s Complement
+2.0
+V
CC
– 1.4
0
+0.8
±10
±10
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
V
V
µA
µA
T
Bits
MIN
TYP
MAX
MIN
DAC715PB, UB
TYP
MAX
MIN
DAC715PK, UK
TYP
MAX
MIN
DAC715PL, UL
TYP
MAX
UNITS
6
4
10
0.005
0.03
3.0
87
2
15
120
10
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
µs
µs
V/µs
%
%
%
dB
nV-s
nV-s
nV√Hz
0 to +10
±5
0.1
Indefinite
+9.975
+9.960
2
Indefinite
+11.4
–16.5
+15
–15
13
22
525
+16.5
–11.4
15
25
600
+10.000
1
+10.025
+10.040
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
V
mA
Ω
V
V
Ω
mA
V
V
mA
mA
mW
°C
°C
°C/W
°C/W
T
Specifications are the same as grade to the left.
NOTES: (1) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (2) FSR means Full Scale Range. For example, for a 0 to +10V output, FSR = 10V.
(3) Errors externally adjustable to zero. (4) Maximum represents greater than the 3σ limit. Not 100% tested for this parameter. (5) For the worst case code changes: FFFF
H
to 0000
H
and 0000
H
to
FFFF
H
. These are Binary Two’s Complement (BTC) codes. (6) Typical supply voltages times maximum currents.
®
DAC715
2
ABSOLUTE MAXIMUM RATINGS
(1)
+V
CC
to COMMON ...................................................................... 0V, +17V
–V
CC
to COMMON ...................................................................... 0V, –17V
+V
CC
to –V
CC ...........................................................................................................................
34V
Digital Inputs to COMMON ..................................................... –1V to +V
CC
External Voltage Applied to BPO and Range Resistors .....................
±V
CC
V
REF OUT
...................................................... Indefinite Short to COMMON
V
OUT
............................................................ Indefinite Short to COMMON
Power Dissipation .......................................................................... 750mW
Storage Temperature ...................................................... –60°C to +150°C
Lead Temperature (soldering, 10s) ................................................ +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
TIMING DIAGRAM
t
AW
A
0
, A
1
t
AH
t
DW
D0-D15
t
DH
WR
t
WP
PACKAGE INFORMATION
PRODUCT
DAC715P
DAC715U
DAC715PB
DAC715UB
DAC715PK
DAC715UK
DAC715PL
DAC715UL
PACKAGE
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
PACKAGE DRAWING
NUMBER
(1)
246
217
246
217
246
217
246
217
TIMING SPECIFICATIONS
T
A
= –40°C to +85°C, +V
CC
= +12V or +15V, –V
CC
= –12V or –15V.
SYMBOL
t
DW
t
AW
t
AH
t
DH
t
WP(1)
t
CP
PARAMETER
Data Valid to End of WR
A
0
, A
1
Valid to End of WR
A
0
, A
1
Hold after End of WR
Data Hold after end of WR
Write Pulse Width
CLEAR Pulse Width
MIN
50
50
10
10
50
200
MAX
UNITS
ns
ns
ns
ns
ns
ns
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
NOTES: (1) For single-buffered operation, t
WP
is 80ns min. Refer to page 10.
TRUTH TABLE
ORDERING INFORMATION
DIFFERENTIAL
LINEARITY
ERROR MAX
at +25
°
C
±4LSB
±4LSB
±2LSB
±2LSB
±2LSB
±2LSB
±1LSB
±1LSB
A
0
0
1
1
0
X
X
A
1
1
0
1
0
X
X
WR
1
→
0
→
1
1
→
0
→
1
1
→
0
→
1
0
1
X
CLR
1
1
1
1
1
0
DESCRIPTION
Load Input Latch
Load D/A Latch
No Change
Latches Transparent
No Change
Reset D/A Latch
PRODUCT
DAC715P
DAC715U
DAC715PB
DAC715UB
DAC715PK
DAC715UK
DAC715PL
DAC715UL
PACKAGE
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
TEMPERATURE
RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-Brown
Corporation recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published speci-
fications.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
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Embedded System
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