Features
•
•
•
•
•
•
•
•
•
Supply Voltage: 5V
Low Power Consumption: 15 mA/5V
Output Level and Spurious Products Adjustable (Optional)
Excellent Sideband Suppression by Means of Duty Cycle Regeneration
of the LO Input Signal
Phase-control Loop for Precise 90° Phase Shifting
Power-down Mode
Low LO Input Level: -15 dBm
50-Ω Single-ended LO and RF Port
LO Frequency Range of 30 MHz to 300 MHz
Benefits
•
Low Current Consumption
•
Few External Components Result in Cost and Board Space Saving
•
Adjustment Free Hence Saves Time
300-MHz
Quadrature
Modulator
U2793B
Electrostatic sensitive device.
Observe precautions for handling.
1. Description
The IC U2793B is a 300-MHz quadrature modulator that uses Atmel
®
’s advanced
UHF process. It features low current consumption, single-ended RF ports and adjust-
ment-free application, which makes the device suitable for all digital radio systems,
e.g., GSM, PCN, JDC and WLAN. As an option, output level and spurious products
are adjustable at pins 19 and 20. In conjunction with Atmel’s U2795B mixer, an
up-converter up to 2 GHz can be realized.
Figure 1-1.
Block Diagram
S
PD
BB
Ai
BB
Ai
10
9
8
PU
1
LO
i
LO
i
14
Duty cycle
15 regenerator
Frequency
doubler
0°
90°
90° control
loop
Σ
Power 6,7 V
S
up
V
Ref
13
19
LP2
LP1
20
RF
o
4
BB
Bi
BB
Bi
11
12
3,16,17,18
GND
2
5
AC
GND
AC
GND
4651E–CELL–07/06
2. Pin Configuration
Figure 2-1.
Pinning SSO20
PU
ACGND
GND
RFO
ACGND
VS
VS
SPU
BBAI
BBAI
1
2
3
4
5
U2793B
6
7
8
9
10
15
14
13
12
11
LOI
LOI
VREF
BBBI
BBBI
20
19
18
17
16
LP1
LP2
GND
GND
GND
2
U2793B
4651E–CELL–07/06
U2793B
Table 2-1.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Description
Symbol
PU
ACGND
GND
RFO
ACGND
VS
VS
SPU
BBAI
BBAI
BBBI
BBBI
VREF
LOI
LOI
GND
GND
GND
LP2
LP1
Function
Power-up input
AC ground
Ground
RF output
AC ground
Supply voltage
Supply voltage
Settling time power-up
Baseband input A
Baseband input A inverse
Baseband input B
Baseband input B inverse
Reference voltage (2.5V)
Input LO
Input LO inverse, typically grounded
Ground
Ground
Ground
Output low pass and power control
Output low pass and power control
3
4651E–CELL–07/06
3. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Supply voltage
Input voltage
Junction temperature
Storage temperature range
Symbol
V
S
V
i
T
j
T
Stg
Value
6
0 to V
S
125
–55 to +125
Unit
V
V
°C
°C
4. Thermal Resistance
Parameters
Junction ambient SSO20
Symbol
R
thJA
Value
140
Unit
K/W
5. Operating Range
Parameters
Supply voltage
Ambient temperature range
Symbol
V
S
T
amb
Value
4.5 to 5.5
–40 to +85
Unit
V
°C
6. Electrical Characteristics
Test conditions (unless otherwise specified); V
S
= 5V, T
amb
= 25°C, referred to test circuit.
System impedance Zo = 50Ω, f
LO
=150 MHz, P
LO
= -15 dBm, V
BBi
= 1.0 V
pp
, differential
No.
1.1
1.2
2
2.1
2.2
2.3
2.4
3
3.1
3.2
3.3
3.4
Parameters
Supply voltage range
Supply current
Baseband Inputs, Pin 9-10, 11-12
Input-voltage range (differential)
Input impedance
Input-frequency range
Input voltage, common mode
LO Input, Pins 14 and 15
Frequency range
Input level
(1)
Input impedance
Voltage standing wave ratio
f
LOi
P
LOi
Z
iLO
VSWR
LO
DCR
LO
0.4
30
–15
(2)
3.5
0.6
300
–5
MHz
dBm
Ω
D
D
D
D
D
V
BBi
Z
BBi
f
BBi
0
2.5
1000
30
50
1500
mVpp
kΩ
MHz
V
D
D
D
Test Conditions
Pin
6, 7
6, 7
Symbol
V
S
I
S
Min.
4.5
Typ.
5
15
Max.
5.5
Unit
V
mA
Type*
A
A
3.5 Duty-cycle range
Notes: 1. Required LO level is a function of the LO frequency.
2. The LO input impedance is consisting of a 50
Ω
resistor in series with a 15 pF capacitor.
3. With the pins 19 and 20 spurious performance especially for low frequency application can be improved by adding a chip
capacitor between LP1 and LP2. In conjunction with a parallel resistor the output level can be adjusted to the following
mixer stage without degration of LO suppression and noise performance which would decrease if the I/Q input level is
reduced.
4. For T
amb
= –40°C to +85°C and V
S
= 4.5V to 5.5V
4
U2793B
4651E–CELL–07/06
U2793B
6. Electrical Characteristics (Continued)
Test conditions (unless otherwise specified); V
S
= 5V, T
amb
= 25°C, referred to test circuit.
System impedance Zo = 50Ω, f
LO
=150 MHz, P
LO
= -15 dBm, V
BBi
= 1.0 V
pp
, differential (Continued)
No.
4
Parameters
RF Output, Pin 4
f
LO
= 150 MHz
V
BBi
= 1 V
pp
, differential
f
LO
= 50 MHz
V
BBi
= 0.3 V
pp
, differential
P
LO
= –20 dBM
–3
P
RFo
LO
RFO
VSWR
RF
SBS
RFo
Pe
Ae
V
BBi
= 2V, V
BBi
= 3V
V
BBi
= V
BBi
= 2.5V
V
PU
≤
0.5V, pins 6, 7
V
PU
= 1V
Pins 1 to 4, C
SPU
= 100 pF
C
LO =
100 pF, C
RFo
= 1 nF
N
FL
35
32
–1
0
45
1.4
45
<1
< ±0.25
–137
–143
2
dB
deg
dB
dBm/Hz
+2
dBm
A/B
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
4.1
Output level
4.2
4.3
4.4
4.5
4.6
4.7
5
5.1
5.2
6
6.1
7
7.1
LO suppression
Voltage standing wave ratio
Sideband suppression
(3)
Phase error
(4)
Amplitude error
Noise floor
Power-up Mode
Supply current
Settling time
Switching Voltage, Pin 1
Power on
Reference Voltage, Pin 13
Voltage range
dB
A
D
A
D
D
D
I
PU
t
SPU
10
10
1
µA
µs
D
D
V
PUON
V
Ref
Zo
Ref
4
2.375
2.5
30
2.625
V
V
Ω
D
A
D
7.2 Output impedance
Notes: 1. Required LO level is a function of the LO frequency.
2. The LO input impedance is consisting of a 50
Ω
resistor in series with a 15 pF capacitor.
3. With the pins 19 and 20 spurious performance especially for low frequency application can be improved by adding a chip
capacitor between LP1 and LP2. In conjunction with a parallel resistor the output level can be adjusted to the following
mixer stage without degration of LO suppression and noise performance which would decrease if the I/Q input level is
reduced.
4. For T
amb
= –40°C to +85°C and V
S
= 4.5V to 5.5V
5
4651E–CELL–07/06
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