Features
•
Supply Voltage 5V
•
Very Low Power Consumption 125 mW
•
Very Good Image Rejection By Means of Phase Control Loop for Precise 90° Phase
•
•
•
•
•
•
Shifting
Duty-cycle Regeneration for Single-ended LO Input Signal
Low LO Input Level –10 dBm
LO Frequency from 70 MHz to 1 GHz
Power-down Mode
25 dB Gain Control
Very Low I/Q Output DC Offset Voltage Typically < 5 mV
1000-MHz
Quadrature
Demodulator
U2794B
Benefits
•
Low Current Consumption
•
Easy to Implement
•
Perfect Performance for Large Variety of Wireless Applications
Electrostatic sensitive device.
Observe precautions for handling.
1. Description
The silicon monolithic integrated circuit U2794B is a quadrature demodulator manu-
factured using Atmel’s advanced UHF technology. This demodulator features a
frequency range from 70 MHz to 1000 MHz, low current consumption, selectable gain,
power-down mode and adjustment-free handling. The IC is suitable for direct conver-
sion and image rejection applications in digital radio systems up to 1 GHz such as
cellular radios, cordless telephones, cable TV and satellite TV systems.
Rev. 4653D–CELL–11/05
3. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Supply voltage
Input voltage
Junction temperature
Storage-temperature range
Symbol
V
S
V
i
T
j
T
stg
Value
6
0 to V
S
+125
–40 to +125
Unit
V
V
°C
°C
4. Thermal Resistance
Parameters
Junction ambient SSO20
Symbol
R
thJA
Value
140
Unit
K/W
5. Operating Range
Parameters
Supply-voltage range
Ambient-temperature range
Symbol
V
S
T
amb
Value
4.75 to 5.25
–40 to +85
Unit
V
°C
4
U2794B
4653D–CELL–11/05
U2794B
6. Electrical Characteristics
Test conditions (unless otherwise specified); V
S
= 5V, T
amb
= 25°C, referred to test circuit
System impedance Z
O
= 50Ω, f
iLO
= 950 MHz, P
iLO
= –10 dBm
No.
1.1
1.2
2
2.1
3
3.1
3.2
4
4.1
4.2
4.3
4.4
4.5
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Notes:
Parameters
Supply-voltage range
Supply current
Power-down Mode
“OFF” mode supply
current
Switch Voltage
“Power ON”
“Power DOWN”
LO Input, LO
in
Frequency range
Input level
Input impedance
Voltage standing
wave ratio
Duty-cycle range
RF Input, RF
in
Noise figure (DSB)
symmetrical output
Frequency range
–1 dB input
compression point
Second order IIP
Third order IIP
LO leakage
Input impedance
at 950 MHz
(3)
at 100 MHz
f
iRF
= f
iLO
±BW
YQ
High gain
Low gain
(4)
(2)
Test Conditions
Pin
5, 6
5, 6
Symbol
V
S
I
S
Min.
4.75
22
Typ.
30
≤
1
20
Max.
5.25
35
Unit
V
mA
µA
µA
V
Type*
A
A
B
D
D
D
D
D
D
D
D
V
PU
≤
0.5V
V
PU
= 1.0 V
(1)
14, 5
6
14
14
17
17
17
17
17
I
SPU
V
PON
V
POFF
f
iLO
P
iLO
Z
iLO
VSWR
LO
DCR
LO
4
1
70
–12
–10
50
1.2
0.4
12
10
40
–8
+3.5
35
+3
+13
≤
–60
≤
–55
500II0.8
1030
2
0.6
1000
–5
V
MHz
dBm
Ω
See
Figure 6-10
See
Figure 6-3
7, 8
7, 8
7, 8
7, 8
7, 8
7, 8
7, 8
NF
f
iRF
P
1dBHG
P
1dBLG
IIP
2HG
IIP
3HG
IIP
3LG
L
OL
Z
iRF
dB
MHz
dBm
dBm
dBm
dBm
ΩIIpF
D
D
D
D
D
D
D
High gain
Low gain
Symmetric input
Asymmetric input
see
Figure 6-10
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
1. During power-down status a load circuitry with DC-isolation to GND is assumed, otherwise a current of I
≈
(VS –0.8V)/RI
has to be added to the above power-down current for each output I, IX, Q, QX.
2. The required LO-Level is a function of the LO frequency (see
Figure 6-6).
3. Measured with input matching. For 950 MHz, the optional transmission line T3 at the RF input may be used for this pur-
pose. Noise figure measurements without using the differential output signal result in a worse noise figure.
4. Using pins 7 and 8 as a symmetric RF input, the second-order IIP can be improved.
5. Due to test board parasitics, this bandwidth may be reduced and not be equal for I, IX, Q, QX. If symmetry and full band-
width is required, the lowpass pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the I/Q outputs can
be increased further by using a resistor between pins 3, 4, 9 and 10. These resistors shunt the internal loads of
RI ~ 5.4 kΩ. The decrease in gain here has to be considered.
6. The internal current of the output emitter followers is 0.6 mA. This reduces the undistorted output voltage swing at a 50Ω
load to approximately 30 mV. For low signal distortion the load impedance should be RI
≥
5 kΩ.
7. Referred to the level of the output vector
I
+
Q
2
2
8. The low-gain status is achieved with an open or high-ohmic pin 11. A recommended application circuit for switching
between high and low gain status is shown in
Figure 6-1.
5
4653D–CELL–11/05
京公网安备 11010802033920号
EEWORLD
