DG884
Vishay Siliconix
8 x 4 Wideband Video Crosspoint Array
FEATURES
Routes Any Input to Any Output
Wide Bandwidth: 300 MHz
Low Crosstalk:
−85
dB @ 5 MHz
Double Buffered TTL-Compatible
Latches with Readback
D
Low r
DS(on)
: 45
W
D
Optional Negative Supply
D
D
D
D
BENEFITS
D
D
D
D
D
D
D
Reduced Board Space
Improved System Bandwidth
Improved Channel Off-Isolation
Simplified Logic Interfacing
Allows Bipolar Signal Swings
Reduced Insertion Loss
High Reliability
APPLICATIONS
D
Wideband Signal Routing and
Multiplexing
D
High-End Video Systems
D
NTSC, PAL, SECAM Switchers
D
Digital Video Routing
D
ATE Systems
DESCRIPTION
The DG884 contains a matrix of 32 T-switches configured in
an 8
4 crosspoint array. Any of the IN/OUT pins may be
used as an input or output. Any of the IN pins may be switched
to any or simultaneously to all OUT pins.
Control data is loaded individually into four Next Event latches.
When all Next Event latches have been programmed, data is
transferred into the Current Event latches via a SALVO
command. Current Event latch data readback is available to
poll array status.
Output disable capabilities make it possible to parallel multiple
DG884s to form larger switch arrays. DIS outputs provide
control signals used to place external buffers in a power saving
mode.
For additional information see applications note AN504
(FaxBack document number 70610).
The DG884 is built on a proprietary D/CMOS process that
combines low capacitance switching DMOS FETs with low
power CMOS control logic and drivers. The ground lines
between adjacent signal input pins help to reduce crosstalk.
The low on-resistance and low on-capacitance of the DG884
make it ideal for video and wideband signal routing.
FUNCTIONAL BLOCK DIAGRAM
IN
1
IN
2
IN
3
IN
4
IN
5
IN
6
IN
7
IN
8
OUT
1
OUT
2
8 4 Switch Matrix
OUT
3
OUT
4
Decode Logic, Switch Drivers
4 Disable Outputs
WR
CS
B
1
B
0
I/O Control
Logic
Current Event Latches
RS
SALVO
Next Event Latches
I/O A
3
Document Number: 70071
S-52433—Rev. G, 20-Dec-04
A
2
A
1
A
0
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1
DG884
Vishay Siliconix
PIN CONFIGURATION AND ORDERING INFORMATION
OUT1
GND
OUT2
GND
OUT3
GND
6
5
4
3
2
1 44 43 42 41 40
IN
2
GND
IN
3
GND
IN
4
GND
IN
5
GND
IN
6
GND
IN
7
OUT4
GND
GND
GND
IN 1
7
8
9
10
11
12
13
14
15
16
17
PLCC and CLCC
Top View
39
38
37
36
35
34
33
32
31
30
29
DGND
V
L
RS
SALVO
WR
A
3
A
2
A
1
A
0
CS
I/O
ORDERING INFORMATION
Temp Range
−40
to 85_C
−55
to 125_C
Package
44-Pin PLCC
44-Pin CLCC
Part Number
DG884DN
DG884AM/883
18 19 20 21 22 23 24 25 26 27 28
GND
IN8
GND
V−
DIS 1
DIS 2
DIS 3
DIS 4
B0
V+
B1
TRUTH TABLE I
RS
1
1
1
1
1
1
1
1
1
1
0
I/O
0
0
0
0
0
0
0
0
1
1
X
CS
1
0
0
0
X
0
X
0
1
0
X
WR
SALVO
1
1
No change to Next Event latches
Actions
Next Event latches loaded as defined in table below
Next Event latches are transparent.
Next Event data latched-in
Data in all Next Event latches is simultaneously loaded into the Current Event latches, i.e., all
new crosspoint addresses change simultaneously when SALVO goes low.
0
1
1
1
X
1
0
1
1
1
0
1
1
1
0
Current Event latches are transparent
Current Event data latched-in
Both next and Current Event latches are transparent
A
0
, A
1
, A
2
, A
3
−
High impedance
A
0
, A
1
, A
2
, A
3
become outputs and reflect the contents of the Current Event latches. B
0,
B
1
determine which Current Event latches are being read
All crosspoints opened (but data in Next Event latches is preserved)
All other states are not recommended.
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Document Number: 70071
S-52433—Rev. G, 20-Dec-04
DG884
Vishay Siliconix
TRUTH TABLE II
WR
B
1
B
0
A
3
A
2
0
0
0
0
1
1
1
1
X
0
0
0
0
1
1
1
1
X
0
0
0
0
1
1
1
1
X
0
0
0
0
1
1
1
1
X
A
1
0
0
1
1
0
0
1
1
X
0
0
1
1
0
0
1
1
X
0
0
1
1
0
0
1
1
X
0
0
1
1
0
0
1
1
X
A
0
0
1
0
1
0
1
0
1
X
0
1
0
1
0
1
0
1
X
0
1
0
1
0
1
0
1
X
0
1
0
1
0
1
0
1
X
Next Event Latches
IN
1
to OUT
1
Loaded
IN
2
to OUT
1
Loaded
IN
3
to OUT
1
Loaded
IN
4
to OUT
1
Loaded
IN
5
to OUT
1
Loaded
IN
6
to OUT
1
Loaded
IN
7
to OUT
1
Loaded
IN
8
to OUT
1
Loaded
Turn Off OUT
1
Loaded
IN
1
to OUT
2
Loaded
IN
2
to OUT
2
Loaded
IN
3
to OUT
2
Loaded
IN
4
to OUT
2
Loaded
IN
5
to OUT
2
Loaded
IN
6
to OUT
2
Loaded
IN
7
to OUT
2
Loaded
IN
8
to OUT
2
Loaded
Turn Off OUT
2
Loaded
IN
1
to OUT
3
Loaded
IN
2
to OUT
3
Loaded
IN
3
to OUT
3
Loaded
IN
4
to OUT
3
Loaded
IN
5
to OUT
3
Loaded
IN
6
to OUT
3
Loaded
IN
7
to OUT
3
Loaded
IN
8
to OUT
3
Loaded
Turn Off OUT
3
Loaded
IN
1
to OUT
4
Loaded
IN
2
to OUT
4
Loaded
IN
3
to OUT
4
Loaded
IN
4
to OUT
4
Loaded
IN
5
to OUT
4
Loaded
IN
6
to OUT
4
Loaded
IN
7
to OUT
4
Loaded
IN
8
to OUT
4
Loaded
Turn Off OUT
4
Loaded
0
0
1
0
0
1
1
0
0
1
0
1
0
1
1
1
0
Note:
When WR = 0 Next Event latches are transparent. Each crosspoint is addressed individually, e.g., to connect IN
1
to OUT
1
thru OUT
4
requires A
0
, A
1
, A
2
= 0 to be latched with each combination of B
0
, B
1
. When RS = 0, all four DIS outputs pull low simultaneously.
ABSOLUTE MAXIMUM RATINGS
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−0.3
V to 21 V
V+ to V− . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−0.3
V to 21 V
V− to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−10
V to 0.3 V
V
L
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to (V+) + 0.3 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V−)
−
0.3 V to (V
L
) + 0.3 V
or 20 mA, whichever occurs first
V
S
, V
D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V−)
−
0.3 V to (V−) + 14 V
or 20 mA, whichever occurs first
CURRENT (any terminal) Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
CURRENT (S or D) Pulsed 1 ms 10% duty . . . . . . . . . . . . . . . . . . . . . . 40 mA
Storage Temperature
(A Suffix) . . . . . . . . . . . . . . . . . . . .
−65
to 150_C
(D Suffix) . . . . . . . . . . . . . . . . . . . .
−65
to 125_C
Operating Temperature
(A Suffix) . . . . . . . . . . . . . . . . . . . .
−55
to 125_C
(D Suffix) . . . . . . . . . . . . . . . . . . . . .
−40
to 85_C
Power Dissipation (Package)
a
44-Pin Quad J Lead PLCC
b
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
44-Pin Quad J Lead Hermetic CLCC
c
. . . . . . . . . . . . . . . . . . . . . . . . 1200 mW
Notes:
a. All leads soldered or welded to PC board.
b. Derate 6 mW/_C above 75_C.
c. Derate 16 mW/_C above 75_C.
Document Number: 70071
S-52433—Rev. G, 20-Dec-04
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DG884
Vishay Siliconix
SPECIFICATIONS
a
Test Conditions
Unless Specified
V+ = 15 V, V− =
−3
V
V
L
= 5 V, RS = 2.0 V
SALVO, CS, WR, I/O = 0.8 V
A Suffix
−55
to 125_C
D Suffix
−40
to 85_C
Parameter
Analog Switch
Analog Signal Range
e
Drain-Source On-Resistance
Resistance Match
Between Channels
Source Off Leakage Current
Drain Off Leakage Current
Total Switch On
Leakage Current
Symbol
Temp
b
Typ
c
Min
d
Max
d
Min
d
Max
d
Unit
V
ANALOG
r
DS(on)
Dr
DS(on)
I
S(off)
I
D(off)
I
D(on)
V− =
−5
V
I
S
=
−10
mA, V
D
= 0 V
V
AIH
= 2 0 V V
AIL
= 0 8 V
2.0 V,
0.8
Sequence Each Switch On
V
S
= 8 V, V
D
= 0 V,
RS = 0.8 V
V
S
= 0 V, V
D
= 8 V,
RS = 0.8 V
V
S
= V
D
= 8 V
Full
Room
Full
Room
Room
Full
Room
Full
Room
Full
45
3
−5
8
90
120
9
−5
8
90
120
9
V
W
−20
−200
−20
−200
−20
−2000
20
200
20
200
20
2000
−20
−200
−20
−200
−20
−200
20
200
20
200
20
200
nA
Digital Input/Output
Input Voltage High
Input Voltage Low
Address Input Current
Address Output Current
DIS Pin Sink Current
V
AIH
V
AIL
I
AI
I
AO
I
DIS
V
AI
= 0 V or 2 V or 5 V
V
AO
= 2.7 V, See Truth Table
V
AO
= 0.4 V, See Truth Table
Full
Full
Room
Full
Room
Room
Room
0.1
−600
1500
1.5
500
−1
−10
2
0.8
1
10
−200
500
mA
−1
−10
2
0.8
1
10
−200
mA
V
Dynamic Characteristics
On State Input Capacitance
e
Off State Input Capacitance
e
Off State
Output Capacitance
e
Transition Time
Break-Before-Make Interval
SALVO, WR Turn On Time
SALVO, WR Turn Off Time
Charge Injection
Matrix Disabled Crosstalk
Adjacent Input Crosstalk
All Hostile Crosstalk
Bandwidth
C
S(on)
C
S(off)
C
D(off)
t
TRANS
t
OPEN
t
ON
t
OFF
Q
X
TALK(DIS)
X
TALK
(
AI)
X
TALK(AH)
BW
See Figure 11
1 In to 1 Out, See Figure 11
1 In to 4 Out, See Figure 11
Room
Room
Room
Room
Room
Full
Room
Full
Room
Full
Room
Room
Room
Room
Room
−100
−82
−85
−66
300
MHz
dB
10
300
500
175
300
30
120
8
10
20
20
40
160
20
20
300
10
300
175
pC
ns
pF
See Figure 5
R
L
= 1 kW , C
L
= 35 pF
50% Control to 90% Output
See Figure 3
See Figure 6
R
IN
= R
L
= 75
W
f = 5 MHz, See Figure 10
R
IN
= 10
W
, R
L
= 10 kW
f = 5 MHz, See Figure 9
R
IN
= 10
W
, R
L
= 10 kW
f = 5 MHz, See Figure 8
R
L
= 50
W
, See Figure 7
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Document Number: 70071
S-52433—Rev. G, 20-Dec-04
DG884
Vishay Siliconix
SPECIFICATIONS
a
Test Conditions
Unless Specified
V+ = 15 V, V− =
−3
V
V
L
= 5 V, RS = 2.0 V
SALVO, CS, WR, I/O = 0.8 V
A Suffix
−55
to 125_C
D Suffix
−40
to 85_C
Parameter
Power Supplies
Positive Supply Current
Negative Supply Current
Digital GND Supply Current
Logic Supply Current
Functional O
Operating S
Supply Volt-
age Range
e
Symbol
Temp
b
Typ
c
Min
d
Max
d
Min
d
Max
d
Unit
I+
I−
I
DG
I
L
V+ to V−
V− to GND
V+ to GND
See Operating Voltage Range
( yp
)
(Typical Characteristics)
page 6
All Inputs At GND or 2 V
RS = 2 V
Room
Full
Room
Full
Full
Full
Full
Full
Full
1.5
−1.5
−275
200
13
−5.5
10
−3
−5
−750
3
6
−3
−5
−750
500
20
0
20
13
−5.5
10
3
6
mA
500
20
0
20
mA
V
Minimum Input Timing Requirements
Address Write Time
Minimum WR Pulse Width
Write Address Time
Chip Select Write Time
Write Chip Select Time
Minimum SALVO
Pulse Width
SALVO Write Time
Write SALVO Time
Input Output Time
Address Output Time
Chip Select Output Time
Chip Select Address Time
Reset to SALVO
I/O Address Input Time
t
AW
t
WP
t
WA
t
CW
t
WC
t
SP
t
SW
t
WS
t
IO
t
AO
t
CO
t
CA
t
RS
t
IA
See Figure 1
Full
Full
Full
Full
Full
Full
Full
Room
Room
Room
Room
Room
Full
Room
50
20
50
−10
50
25
50
−10
20
150
150
150
60
50
200
200
200
50
100
10
100
75
100
10
50
100
10
100
75
100
10
50
200
200
200
100
50
ns
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
Document Number: 70071
S-52433—Rev. G, 20-Dec-04
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