11274-502-XTP datasheet, PDF - EEWORLD Datasheet

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11274-502-XTP: DescriptionPLL FREQUENCY SYNTHESIZER, 28MHz, PDSO16, 0.150 INCH, GREEN, SOIC-16; CategoryAnalog mixed-signal IC The signal circuit; File Size1MB，43 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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11274-502-XTP Overview

PLL FREQUENCY SYNTHESIZER, 28MHz, PDSO16, 0.150 INCH, GREEN, SOIC-16

11274-502-XTP Parametric

Parameter Name	Attribute value
Parts packaging code	SOIC
package instruction	SOP,
Contacts	16
Reach Compliance Code	unknow
Analog Integrated Circuits - Other Types	PLL FREQUENCY SYNTHESIZER
JESD-30 code	R-PDSO-G16
JESD-609 code	e3/e4
length	9.89 mm
Number of functions	1
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.73 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN/NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	3.9 mm
Base Number Matches	1

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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC

Data Sheet

1.0 Features

•

Complete programmable control via I

C™-bus

Selectable CMOS or PECL compatible outputs

External feedback loop capability allows genlocking

Tunable VCXO loop for jitter attenuation

2.0 Description

The FS6131-01 is a monolithic CMOS clock generator/regenerator IC designed to minimize cost and component count in a variety of

electronic systems. Via the I C-bus interface, the FS6131-01 can be adapted to many clock generation requirements.

The ability to tune the on-board voltage-controlled crystal oscillator (VCXO), the length of the reference and feed-back dividers, their

granularity, and the flexibility of the post divider make the FS6131-01 the most flexible stand-alone phase-locked loop (PLL) clock

generator available.

3.0 Applications

•

Frequency synthesis

Line-locked and genlock applications

Clock multiplication

Telecom jitter attenuation

SCL

SDA

ADDR

VSS

XIN

XOUT

XTUNE

VDD

CLKN

CLKP

VDD

FBK

REF

VSS

EXTLF

LOCK/IPRG

FS6131

16-pin 0.150" SOIC

Figure 1: Pin Configuration

AMI Semiconductor

– Rev. 3.0, Jan. 08

www.amis.com

Specifications subject to change without notice

FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC

Data Sheet

4.0 Functional Block Description

4.1 Main Loop PLL

The main loop phase locked loop (ML-PLL) is a standard phase- and frequency- locked loop architecture. As shown in Figure 2, the

ML-PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled

oscillator (VCO), a feedback divider, and a post divider.

During operation, the reference frequency (f

REF

), generated by either the on-board crystal oscillator or an external frequency source, is

first reduced by the reference divider. The integer value that the frequency is divided by is called the modulus, and is denoted as N

for

the reference divider. The divided reference is then fed into the PFD.

The PFD controls the frequency of the VCO (f

VCO

) through the charge pump and loop filter. The VCO provides a high-speed, low noise,

continuously variable frequency clock source for the ML-PLL. The output of the VCO is fed back to the PFD through the feedback

divider (the modulus is denoted by N

) to close the loop.

The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at

the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is

VCO

REF

If the VCO frequency is used as the PLL output frequency (f

CLK

) then the basic PLL equation can be rewritten as

⎛

⎞

CLK

REF

⎜

⎟

⎜

⎟

⎝

⎠

4.1.1 Reference Divider

The reference divider is designed for low phase jitter. The divider accepts either the output of either the crystal loop (the VCXO output)

or an external reference frequency, and provides a divided-down frequency to the PFD. The reference divider is a 12-bit divider, and

can be programmed for any modulus from 1 to 4095. See both Table 3 and Table 8 for additional programming information.

4.1.2 Feedback Divider

The feedback divider is based on a dual-modulus pre-scaler technique. The technique allows the same granularity as a fully

programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also

called a prescaler) is placed between the VCO and the programmable feedback divider because of the high speeds at which the VCO

can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall

power consumption of the divider.

For example, a fixed divide-by-eight could be used in the feedback divider. Unfortunately, a divide-by-eight would limit the effective

modulus of the feedback divider path to multiples of eight. The limitation would restrict the ability of the PLL to achieve a desired input-

frequency-to-output frequency ratio without making both the reference and feedback divider values comparatively large. Large divider

moduli are generally undesirable due to increased phase jitter.

vco

Dual-

Modulus

Prescaler

Counter

Figure 3: Feedback Divider

AMI Semiconductor

– Rev. 3.0, Jan. 08

www.amis.com

Specifications subject to change without notice

11274-502-XTP Related Products

	11274-502-XTP	11274-502-XTD	0603Y223KAHWD04	1206Y123KACB	11274-901-XTP	FS6131-01I
Description	PLL FREQUENCY SYNTHESIZER, 28MHz, PDSO16, 0.150 INCH, GREEN, SOIC-16	PLL FREQUENCY SYNTHESIZER, 28MHz, PDSO16, 0.150 INCH, GREEN, SOIC-16	Ceramic Capacitor, Multilayer, Ceramic, 50V, 10% +Tol, 10% -Tol, X7R, 15% TC, 0.022uF, Surface Mount, 0603, CHIP	Ceramic Capacitor, Ceramic, 50V, 10% +Tol, 10% -Tol, X7R, -/+15ppm/Cel TC, 0.012uF, 1206,	230MHz, OTHER CLOCK GENERATOR, PDSO16, 0.150 INCH, SOIC-16	IC,MISCELLANEOUS CLOCK GENERATOR,CMOS,SOP,16PIN,PLASTIC
package instruction	SOP,	SOP,	, 0603	, 1206	SOP,	SOIC-16
Reach Compliance Code	unknow	unknow	compliant	compliant	unknown	unknow
Number of terminals	16	16	2	2	16	16
Maximum operating temperature	70 °C	70 °C	125 °C	125 °C	85 °C	85 °C
Minimum operating temperature	-	-	-55 °C	-55 °C	-40 °C	-40 °C
JESD-30 code	R-PDSO-G16	R-PDSO-G16	-	-	R-PDSO-G16	R-PDSO-G16
length	9.89 mm	9.89 mm	-	3.2 mm	9.9 mm	9.89 mm
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	-	-	SOP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR PACKAGE	-	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	-	SMT	SMALL OUTLINE	SMALL OUTLINE
Maximum seat height	1.73 mm	1.73 mm	-	-	1.75 mm	1.73 mm
surface mount	YES	YES	YES	-	YES	YES
technology	CMOS	CMOS	-	-	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	-	-	INDUSTRIAL	INDUSTRIAL
Terminal surface	MATTE TIN/NICKEL PALLADIUM GOLD	MATTE TIN/NICKEL PALLADIUM GOLD	TIN LEAD SILVER OVER NICKEL	Tin (Sn)	-	-
Terminal form	GULL WING	GULL WING	-	-	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	-	-	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	-	-	DUAL	DUAL
width	3.9 mm	3.9 mm	-	1.6 mm	3.9 mm	3.9 mm
ECCN code	-	-	EAR99	EAR99	EAR99	EAR99

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