EEWORLDEEWORLDEEWORLD

Part Number

Search

CY28341

Description
Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems
File Size192KB,21 Pages
ManufacturerCypress Semiconductor
Download Datasheet Compare View All

CY28341 Overview

Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems

CY28341
Universal Single-Chip Clock Solution for VIA P4M266/KM266
DDR Systems
Features
Supports VIA P4M266/KM266 chipsets
Supports Pentium® 4, Athlon™ processors
Supports two DDR DIMMS
Supports three SDRAMS DIMMS at 100 MHz
Provides:
— Two different programmable CPU clock pairs
— Six differential SDRAM DDR pairs
— Three low-skew/low-jitter AGP clocks
— Seven low-skew/low-jitter PCI clocks
— One 48M output for USB
— One programmable 24M or 48M for SIO
Dial-a-Frequency™ and Dial-a-dB features
Spread Spectrum for best electromagnetic interference
(EMI) reduction
Watchdog feature for systems recovery
SMBus-compatible for programmability
56-pin SSOP and TSSOP packages
Table 1. Frequency Selection Table
FS(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1100
1111
CPU
66.80
100.00
120.00
133.33
72.00
105.00
160.00
140.00
77.00
110.00
180.00
150.00
90.00
100.00
200.00
133.33
AGP
66.80
66.80
60.00
66.67
72.00
70.00
64.00
70.00
77.00
73.33
60.00
60.00
60.00
66.67
66.67
66.67
PCI
33.40
33.40
30.00
33.33
36.00
35.00
32.00
35.00
38.50
36.67
30.00
30.00
30.00
33.33
33.33
33.33
Block Diagram
XIN
XOUT
XTAL
REF0
VDDR
REF(0:1)
VDDI
CPUCS_T/C
FS0
Pin Configuration
[1]
*FS0/REF0
VSSR
XIN
XOUT
VDDAGP
AGP0
*SELP4_K7/AGP1
AGP2
VSSAGP
**FS1/PCI_F
**SELSDR_DDR/PCI1
*MULTSEL/PCI2
VSSPCI
PCI3
PCI4
VDDPCI
PCI5
PCI6
VSS48M
**FS3/48M
**FS2/24_48M
VDD48M
VDD
VSS
IREF
*PD#/SRESET#
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VTTPWRGD#/REF1
VDDR
VSSC
CPUT/CPUOD_T
CPUC/CPUOD_C
VDDC
VDDI
CPUCS_C
CPUCS_T
VSSI
FBOUT
BUF_IN
DDRT0/SDRAM0
DDRC0/SDRAM1
DDRT1/SDRAM2
DDRC1/SDRAM3
VDDD
VSSD
DDRT2/SDRAM4
DDRC2/SDRAM5
DDRT3/SDRAM6
DDRC3/SDRAM7
VDDD
VSSD
DDRT4/SDRAM8
DDRC4/SDRAM9
DDRT5/SDRAM10
DDRC5/SDRAM11
SELP4_K7#
VDDC
CPU(0:1)/CPU0D_T/C
VDDPCI
FS2
PLL1
FS3 FS1
PCI(3:6)
PCI_F
MULTSEL
PCI2
PCI1
VDDAGP
AGP(0:2)
VDD48M
48M
/2
PD#
SDATA
SCLK
SMBus
PLL2
WDEN
24_48M
WD
SELSDR_DDR
Buf_IN
S2D
CONVERT
SRESET#
VDDD
FBOUT
DDRT(0:5)/SDRAM(0,2,4,6,8,10)
DDRC(0:5)/SDRAM(1,3,5,7,9,11)
56 pin SSOP
Note:
1. Pins marked with [*] have internal pull-up resistors. Pins marked with [**] have internal pull-down resistors.
Cypress Semiconductor Corporation
Document #: 38-07367 Rev. *A
3901 North First Street
San Jose
CA 95134 • 408-943-2600
Revised December 26, 2002
C Y 283 41

CY28341 Related Products

CY28341
Description Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems
【Help】 Union and structure
typedef union dip{ struct{ unsigned int a: 1;unsigned int b: 1;unsigned int c: 1; unsigned int d: 1;unsigned int e: 1;unsigned int f: 1;unsigned int g: 1;unsigned int h: 1;}bit;unsigned char dip_switc...
daozhang Microcontroller MCU
Emergency assistance
Can anyone help me design a course on making an electronic clock using Multisim2001 and Protel99? Thank you~~~ Email: ll3511@126.com...
rabbitni Talking
Sharing of buzzer program based on 430f5529
The microcontroller source program is as follows: #include "msp430f5529.h" long unsigned int n; void delay(unsigned int x) {int i,j;for(i=x;i0;i--)for(j=110;j0;j--); } #define K1 (P2INBIT1) int flag =...
火辣西米秀 Microcontroller MCU
STM32 uses FSMC to drive ILI9320 problem
The LCD is driven, but there are obvious bright lines when sending monochrome test data. What should I do?...
hl449006540 stm32/stm8
CAN bus and its application technology
1 Introduction to CAN bus and its characteristicsCAN network (Controller Area Network) is a type of fieldbus technology. It is a new generation of network communication protocol with an open architect...
frozenviolet Automotive Electronics
The Business Value of DFM
The use of DFM not only determines whether the design can be manufactured, but also determines whether the design can be manufactured efficiently and profitably. DFM can enable us to make the design m...
vayo123 PCB Design

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1744  113  1746  1790  427  36  3  37  9  30 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号