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PAL20R8-7PC

Description
OT PLD, 25 ns, CDIP24
CategoryProgrammable logic devices    Programmable logic   
File Size2MB,45 Pages
ManufacturerAMD
Websitehttp://www.amd.com
Download Datasheet Parametric View All

PAL20R8-7PC Overview

OT PLD, 25 ns, CDIP24

PAL20R8-7PC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerAMD
Parts packaging codeDIP
package instructionDIP, DIP24,.3
Contacts24
Reach Compliance Codeunknow
Other featuresPOWER-UP RESET; 1 EXTERNAL CLOCK; REGISTER PRELOAD
ArchitecturePAL-TYPE
maximum clock frequency74 MHz
JESD-30 codeR-PDIP-T24
JESD-609 codee0
length30.734 mm
Dedicated input times12
Number of I/O lines
Number of entries12
Output times8
Number of product terms64
Number of terminals24
Maximum operating temperature75 °C
Minimum operating temperature
organize12 DEDICATED INPUTS, 0 I/O
Output functionREGISTERED
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP24,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Programmable logic typeOT PLD
propagation delay8 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL EXTENDED
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
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