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FSDL0365RNB, FSDM0365RNB
Features
• Internal Avalanche Rugged Sense FET
• Consumes only 0.65W at 240VAC & 0.3W load with
Advanced Burst-Mode Operation
• Frequency Modulation for EMI Reduction
• Precision Fixed Operating Frequency
• Internal Start-up Circuit
• Pulse-by-Pulse Current Limiting
• Over Voltage Protection (OVP)
• Over Load Protection (OLP)
• Internal Thermal Shutdown Function (TSD)
• Auto-Restart Mode
• Under Voltage Lockout (UVLO)
• Low Operating Current (3mA)
• Adjustable Peak Current Limit
• Built-in Soft Start
Green Mode Fairchild Power Switch (FPS
TM
)
OUTPUT POWER TABLE
230VAC
±15%
(3)
PRODUCT
FSDM0265RNB
FSDL0365RNB
FSDM0365RNB
Adapt-
er
(1)
16W
19W
19W
Open
Frame
(2)
27W
30W
30W
85-265VAC
Adapt-
er
(1)
13W
16W
16W
Open
Frame
(2)
20W
24W
24W
Applications
• SMPS for VCR, SVR, STB, DVD & DVCD Player
• SMPS for Printer, Facsimile & Scanner
• Adapter for Camcorder
Notes:
1. Typical continuous power in a non-ventilated enclosed
adapter with sufficient drain pattern as a heat sinker, at
50°C ambient.
2. Maximum practical continuous power in an open frame
design with sufficient drain pattern as a heat sinker, at 50°C
ambient.
3. 230 VAC or 100/115 VAC with doubler.
Typical Circuit
Related Application Notes
• AN-4137, 4141, 4147(Flyback) / AN-4134(Forward)
Description
Each product in the FSDx0365RNB (x for L, M) family con-
sists of an integrated Pulse Width Modulator (PWM) and
Sense FET, and is specifically designed for high performance
off-line Switch Mode Power Supplies (SMPS) with minimal
external components. Both devices are integrated high voltage
power switching regulators which combine an avalanche rug-
ged Sense FET with a current mode PWM control block. The
integrated PWM controller features include: a fixed oscillator
with frequency modulation for reduced EMI, Under Voltage
Lock Out (UVLO) protection, Leading Edge Blanking (LEB),
an optimized gate turn-on/turn-off driver, Thermal Shut Down
(TSD) protection and temperature compensated precision cur-
rent sources for loop compensation and fault protection cir-
cuitry. The FSDx0365RNB offers better performance in Soft
Start than FSDx0365RN. When compared to a discrete MOS-
FET and controller or RCC switching converter solution, the
FSDx0365RNB devices reduce total component count, design
size, weight while increasing efficiency, productivity, and sys-
tem reliability. Both devices provide a basic platform that is
well suited for the design of cost-effective flyback converters.
FPS
TM
is a trademark of Fairchild Semiconductor Corporation.
©2005 Fairchild Semiconductor Corporation
AC
IN
DC
OUT
Vstr
Ipk
PWM
Vfb
Drain
Vcc
Source
Figure 1. Typical Flyback Application
Rev.1.0.4
FSDL0365RNB, FSDM0365RNB
Internal Block Diagram
Vcc
2
+
Vstr
5
Drain
6,7,8
I
CH
8V/12V
Vcc
V
BURH
-
Vcc good
Freq.
Modulation
OSC
Vref
V
BURL
/V
BURH
I
BUR(pk)
Vcc
I
DELAY
Vcc
I
FB
Internal
Bias
Vfb
3
Normal
PWM
Burst
S
R
Q
Q
2.5R
Ipk
4
R
Gate
driver
LEB
V
SD
Vcc
Vovp
Vcc good
TSD
S
R
Q
Q
1 GND
Soft Start
Figure 2. Functional Block Diagram of FSDx0365RNB
2
FSDL0365RNB, FSDM0365RNB
Pin Definitions
Pin Number
1
Pin Name
GND
Pin Function Description
Sense FET source terminal on primary side and internal control ground.
Positive supply voltage input. Although connected to an auxiliary transform-
er winding, current is supplied from pin 5 (Vstr) via an internal switch during
startup (see Internal Block Diagram section). It is not until Vcc reaches the
UVLO upper threshold (12V) that the internal start-up switch opens and de-
vice power is supplied via the auxiliary transformer winding.
The feedback voltage pin is the non-inverting input to the PWM comparator.
It has a 0.9mA current source connected internally while a capacitor and op-
tocoupler are typically connected externally. A feedback voltage of 6V trig-
gers over load protection (OLP). There is a time delay while charging
external capacitor Cfb from 3V to 6V using an internal 5uA current source.
This time delay prevents false triggering under transient conditions, but still
allows the protection mechanism to operate under true overload conditions.
This pin adjusts the peak current limit of the Sense FET. The feedback
0.9mA current source is diverted to the parallel combination of an internal
2.8kΩ resistor and any external resistor to GND on this pin to determine the
peak current limit. If this pin is tied to Vcc or left floating, the typical peak cur-
rent limit will be 2.15A.
This pin connects directly to the rectified AC line voltage source. At start up
the internal switch supplies internal bias and charges an external storage
capacitor placed between the Vcc pin and ground. Once the Vcc reaches
12V, the internal switch is opened.
The drain pins are designed to connect directly to the primary lead of the
transformer and are capable of switching a maximum of 650V. Minimizing
the length of the trace connecting these pins to the transformer will decrease
leakage inductance.
2
Vcc
3
Vfb
4
Ipk
5
Vstr
6, 7, 8
Drain
Pin Configuration
8DIP
GND 1
Vcc 2
Vfb 3
Ipk 4
8 Drain
7 Drain
6 Drain
5 Vstr
Figure 3. Pin Configuration (Top View)
3
FSDL0365RNB, FSDM0365RNB
Absolute Maximum Ratings
(Ta=25°C, unless otherwise specified)
Characteristic
Drain Pin Voltage
Vstr Pin Voltage
Drain Current Pulsed
(1)
Single Pulsed Avalanche Energy
(2)
Supply Voltage
Feedback Voltage Range
Total Power Dissipation
Operating Junction Temperature
Operating Ambient Temperature
Storage Temperature
Symbol
V
DRAIN
V
STR
I
DM
E
AS
V
CC
V
FB
P
D
T
J
T
A
T
STG
Value
650
650
12.0
127
20
-0.3 to V
CC
1.56
Internally limited
-25 to +85
-55 to +150
Unit
V
V
A
mJ
V
V
W
°C
°C
°C
Note:
1. Repetitive rating: Pulse width is limited by maximum junction temperature
2. L = 51mH, starting Tj = 25°C
Thermal Impedance
(Ta=25°C, unless otherwise specified)
Parameter
8DIP
Junction-to-Ambient Thermal
(1)
Junction-to-Case Thermal
(2)
Junction-to-Top Thermal
(3)
Symbol
Value
80.01
18.85
33.70
Unit
°C/W
°C/W
°C/W
θ
JA
θ
JC
ψ
JT
Note:
1. Free standing with no heatsink; Without copper clad.
/ Measurement Condition : Just before junction temperature T
J
enters into OTP.
2. Measured on the DRAIN pin close to plastic interface.
3. Measured on the PKG top surface.
- all items are tested with the standards JESD 51-2 and 51-10 (DIP).
4
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