DICE/DWF SPECIFICATION
LTC6268-10
4GHz Ultra-Low Bias
Current FET Input Op Amp
5
4
7
6
PAD FUNCTION
1.
2.
3.
4.
5.
6.
7.
8.
9.
V
–
+IN
–IN
SHDN
V
+
V
+
OUT
V
–
SHDN
DIE CROSS REFERENCE
LTC
®
Finished
Part Number
LTC
®
6268-10
Order
Part Number
LTC6268-10 DICE/DWF
Please refer to LTC standard product data sheet for
other applicable product information.
*DWF = DICE in wafer form.
3
2
1
8
9
50mils
×
29mils,
28mils thick.
Backside metal: None
Backside potential: V
–
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Absolute MAxiMuM RAtings
(Note 1)
Supply Voltage V
+
to V
–
...........................................5.5V
Input Voltage ...............................V
–
– 0.2V to V
+
+ 0.2V
Input Current (+IN, –IN) (Note 2) ...........................±1mA
Input Current (SHDN) ............................................±1mA
Output Current (I
OUT
) (Note 4, 5) .........................135mA
Dice/DWF electRicAl test liMits
V
CM
= mid-supply), R
L
= 1kΩ, V
SHDN
is unconnected.
SYMBOL PARAMETER
Input Offset Voltage
V
OS
I
B
I
OS
CMRR
IVR
PSRR
Input Bias Current
(Notes 3, 4)
Input Offset Current (Notes 3, 4)
Common Mode Rejection Ratio
Input Voltage Range
Power Supply Rejection Ratio
Supply Voltage Range
Specifications are at T
A
= 25°C, V
SUPPLY
= 5.0V (V
+
= 5V, V
–
= 0V,
MIN
–0.7
–1.0
–20
–20
–40
72
64
–0.1
78
3.1
MAX
0.7
1.0
20
20
40
UNITS
mV
mV
fA
fA
fA
dB
dB
V
dB
CONDITIONS
V
CM
= 2.75V
V
CM
= 4.0V
V
CM
= 2.75V
V
CM
= 4.0V
V
CM
= 2.75V
V
CM
= 0.5V to 3.2V (PNP Side)
V
CM
=
–0.1V
to 4.5V
Guaranteed by CMRR
V
CM
= 1.0V, V
SUPPLY
Ranges from 3.1V to 5.25V
4.5
5.25
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1
DICE/DWF SPECIFICATION
LTC6268-10
Dice/DWF electRicAl test liMits
V
CM
= mid-supply), R
L
= 1kΩ, V
SHDN
is unconnected.
SYMBOL PARAMETER
Open Loop Voltage Gain
A
V
I
SC
I
S
I
SHDN
V
IL
V
IH
I
LEAK
Output Short Circuit Current (Note 5)
Supply Current Per Amplifier
Supply Current in Shutdown
(Per Amplifier)
Shutdown Pin Current
SHDN
Input Low Voltage
SHDN
Input High Voltage
Output Leakage Current in Shutdown
Specifications are at T
A
= 25°C, V
SUPPLY
= 5.0V (V
+
= 5V, V
–
= 0V,
MIN
125
10
60
15
MAX
UNITS
V/mV
V/mV
mA
mA
mA
µA
µA
V
V
nA
nA
CONDITIONS
V
OUT
= 0.5V to 4.5V
R
LOAD
= 10k
R
LOAD
= 100
18
0.85
12
12
0.75
400
400
V
SHDN
= 0.75V
V
SHDN
=1.50V
Disable
Enable. If
SHDN
is Unconnected, Amp is Enabled
V
SHDN
= 0V, V
OUT
= 0V
V
SHDN
= 0V, V
OUT
= 5V
–12
–12
1.5
Dice/DWF electRicAl test liMits
V
CM
= mid-supply), R
L
= 1kΩ, V
SHDN
is unconnected.
SYMBOL PARAMETER
Input Offset Voltage
V
OS
I
B
I
OS
CMRR
IVR
A
V
I
SC
I
S
I
SHDN
V
IL
V
IH
Input Bias Current (Notes 3, 4)
Input Offset Current (Notes 3, 4)
Common Mode Rejection Ratio
Input Voltage Range
Open Loop Voltage Gain
Output Short Circuit Current (Note 5)
Supply Current per Amplifier
Supply Current in Shutdown
(Per Amplifier)
Shutdown Pin Current
SHDN
Input Low Voltage
SHDN
Input High Voltage
Specifications are at T
A
= 25°C, V
SUPPLY
= 3.3V (V
+
= 3.3V, V
–
= 0V,
MIN
–0.7
–1.0
–20
–20
–40
63
60
–0.1
80
10
50
14.5
MAX
0.7
1.0
20
20
40
UNITS
mV
mV
fA
fA
fA
dB
dB
V
V/mV
V/mV
mA
mA
mA
µA
µA
V
V
CONDITIONS
V
CM
= 1.0V
V
CM
= 2.3V
V
CM
= 1.0V
V
CM
= 2.3V
V
CM
= 1.0V
V
CM
= 0.5V to 1.2V (PNP Side)
V
CM
=
–0.1V
to 2.8V (Full Range)
Guaranteed by CMRR
V
OUT
= 0.5V to 2.8V
R
LOAD
= 10k
R
LOAD
= 100
2.8
17.5
0.6
12
12
0.75
V
SHDN
= 0.75V
V
SHDN
= 1.5V
Disable
Enable. If
SHDN
is Unconnected, Amp Is Enabled
–12
–12
1.5
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
The inputs are protected by two series connected ESD protection
diodes to each power supply. The input current should be limited to less
than 1mA. The input voltage should not exceed 200mV beyond the power
supply.
Note 3:
The input bias current is the average of the currents into the
positive and negative input pins.
Note 4:
This parameter is specified by design and/or characterization and
is not tested in production.
Note 5:
The LTC6268-10 is capable of producing peak output currents
in excess of 135mA. Current density limitations within the IC require the
continuous current supplied by the output (sourcing or sinking) over
the operating lifetime of the part be limited to under 135mA (Absolute
Maximum).
Wafer level testing is performed per the indicated specifications for dice. Considerable differences in performance can often be observed for dice versus
packaged units due to the influences of packaging and assembly on certain devices and/or parameters. Please consult factory for more information
on dice performance and lot qualifications via lot sampling test procedures.
Dice data sheet subject to change. Please consult factory for current revision in production.
2
I.D.No. 16-33-6268
Linear Technology Corporation
(408) 432-1900
●
FAX:
(408) 434-0507
●
LT 0715 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
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