Multiple Output MEMS PCIe Gen1/2/3/4 Clocks for Automotive
Features
• Automotive AEC-Q100 Qualified
• Complies with PCIe Gen1/2/3/4
• Integrated MEMS Resonator Eliminates the Need
for External 25 MHz Crystal
• Wide Temperature Range:
- Automotive Grade 2: –40°C to +105°C
- Automotive Grade 3: –40°C to +85°C
• 100 MHz HCSL/LVDS/LVPECL/LVCMOS Options
Available
• Small Footprints:
- 14-Lead QFN (DSA557-03, Two Outputs)
- 20-Lead VQFN (DSA557-04, Three Outputs;
DSA557-05, Four Outputs)
• Excellent Shock and Vibration Immunity
- Qualified to MIL-STD-883
• High Reliability
- 20x Better MTF than Quartz Oscillators
• Low Current Consumption: 30% Lower than
Competing Devices
• Supply Range of 2.25V to 3.63V
• Lead-Free and RoHS Compliant
General Description
The DSA557 series of high performance PCI Express
clock generators use a proven silicon MEMS
technology to provide 100 MHz differential output
clocks with excellent jitter and stability over a wide
range of supply voltages and temperatures. By
eliminating the need for quartz or SAW technology,
MEMS oscillators significantly enhance reliability and
accelerate product development, while meeting
stringent clock performance criteria for a variety of
communications, storage, and networking applications.
The DSA557-03/04/05 have two, three, and four
100 MHz outputs, respectively. All have output
enable/disable features.
The DSA557-03 is available in a space-saving 14-lead
QFN package. The DSA557-04 and DSA557-05 are
available in a 20-lead VQFN.
Additional output formats are available in any
combination of LVPECL, LVDS, and HCSL.
Applications
•
•
•
•
Automotive Infotainment
Automotive ADAS
Autonomous Driving
In-Vehicle Network
Benefits
• Replace High Temperature Crystals and Quartz
Oscillators
2019 Microchip Technology Inc.
DS20006175A-page 1
DSA557-03/04/05
Package Types
DSA557-03
14-Lead QFN
(Top View)
VDD0
VDD1
NC
DSA557-04
20-Lead VQFN
(Top View)
CLK2+
CLK2-
VDD
NC
NC
NC
DSA557-05
20-Lead VQFN
(Top View)
CLK3+
CLK2+
CLK3-
CLK2-
VDD
NC
14
OE
NC
NC
VSS
1
2
3
4
5
NC
13
12
11
10
9
8
CLK0+
CLK0-
CLK1-
CLK1+
20
OE1
NC
VSS
VSS
1
2
3
4
5
19
18
17
16
15
14
13
12
11
VSS
VSS
NC
OE2
OE1
NC
VSS
VSS
1
2
3
4
20
19
18
17
16
15
14
13
12
11
VSS
VSS
NC
OE2
5
CLK0-
6
CLK0+
7
CLK1-
8
CLK1+
9
VDD
10
NC
6
7
8
9
10
CLK0-
CLK1-
VDD
CLK0+
6
NC
7
NC
Block Diagrams
DSA557-03
DSA557-04
CLK0+
CLK0-
Output
Control
and
Divider
CLK1+
CLK1-
CLK2-
CLK2+
Control Circuitry
CLK0+
CLK0-
OE1
OE2
CLK1+
NC
Control Circuitry
MEMS
PLL
Output
Control
and
Divider
MEMS
PLLs
OE
CLK1-
CLK1+
DSA557-05
Note:
CLK0+/–, CLK1+/–, CLK2+/–, and CLK3+/–
are 100 MHz, per PCIe standards.
DS20006175A-page 2
2019 Microchip Technology Inc.
DSA557-03/04/05
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Input Voltage .................................................................................................................................... –0.3V to V
DD
+ 0.3V
Supply Voltage .......................................................................................................................................... –0.3V to +4.0V
ESD Protection on All Pins (HBM) .............................................................................................................................4 kV
ESD Protection on All Pins (CDM) ..........................................................................................................................1.5 kV
† Notice:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Electrical Characteristics:
Unless otherwise specified, T = +25°C, V
DD
= 3.3V.
Parameter
Supply Voltage
Supply Current, DSA557-03
Supply Current, DSA557-04
Supply Current, DSA557-05
Frequency Stability (including
frequency variations due to
initial tolerance, temp., and
power supply voltage)
Aging - 1st Year
Startup Time (Note
2)
Input Logic Levels
Input Logic High
Input Logic Low
Output Disable Time (Note
3)
Output Enable Time
Enable Pull-Up Resistor
(Note
4)
HCSL Outputs (Note
5)
Output Logic High
Output Logic Low
Peak-to-Peak Output Swing
Output Transition Time
(Note
6)
Output Duty Cycle
Period Jitter (Note
7)
V
OH
V
OL
—
t
r
/t
f
SYM
J
PER
0.725
—
—
200
48
—
—
—
750
—
—
2.5
—
0.1
—
400
52
—
V
V
mV
ps
%
ps
RMS
R
L
= 50Ω
R
L
= 50Ω
Single-Ended
20% to 80%, R
L
= 50Ω, C
L
= 2 pF
Differential
f
01
= f
02
= 100 MHz
V
IH
V
IL
t
DS
t
EN
—
0.75 x
V
DD
—
—
—
—
—
—
—
—
40
—
0.25 x
V
DD
5
20
—
V
V
ns
ns
kΩ
—
—
—
—
Internally pulled up
Symbol
V
DD
I
DD
I
DD
I
DD
Min.
2.25
—
—
—
—
—
—
—
Δf
Δf
t
SU
—
—
—
Typ.
—
21
60
42
100
42
120
—
—
—
—
Max.
3.63
23
—
46
—
46
—
±100
±50
±5
5
ppm
ppm
ms
All temperature ranges
±1 ppm each subsequent year
T = +25°C
Units
V
mA
Conditions
Note 1
EN pin low, output disabled
EN pin high, output enabled
EN pin low, output disabled
EN pin high, output enabled
EN pin low, output disabled
EN pin high, output enabled
2019 Microchip Technology Inc.
DS20006175A-page 3
DSA557-03/04/05
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics:
Unless otherwise specified, T = +25°C, V
DD
= 3.3V.
Parameter
Symbol
T
J
Jitter, Phase (Common Clock
Architecture)
J
RMS-CCHF
Min.
—
—
—
—
—
—
—
—
Typ.
23
2.20
0.08
0.37
200
2.15
0.06
0.32
Max.
86
3.1
3.0
1.0
500
4.0
7.5
1.0
Units
ps
PP
ps
RMS
ps
RMS
ps
RMS
fs
RMS
ps
RMS
ps
RMS
ps
RMS
Conditions
PCIe Gen 1.1, (Note
8)
T
J
= D
J
+ 14.069 x R
J
(BER 10
-12
)
PCIe Gen 2.1, 1.5 MHz to Nyquist,
(Note
8)
PCIe Gen 2.1, 10 kHz to 1.5 MHz,
(Note
8)
PCIe Gen 3.0, (Note
8)
PCIe Gen 4.0, 16 GHz
PCIe Gen 2.1, 1.5 MHz to Nyquist,
(Note
8)
PCIe Gen 2.1, 10 kHz to 1.5 MHz,
(Note
8)
PCIe Gen 3.0, (Note
8)
J
RMS-CCLF
J
RMS-CC
J
RMS-CC
J
RMS-DCHF
Integrated Phase Noise (Data
Clock Architecture)
J
RMS-DCLF
J
RMS-DC
Note 1:
2:
3:
4:
5:
6:
7:
8:
Each pin V
DD
should be filtered with a 0.1 μF capacitor.
t
SU
is time to 100 ppm of output frequency after V
DD
is applied and outputs are enabled.
Output Waveform and Test Circuit figures define the parameters.
Output is enabled if pad is floated or not connected.
Contact Microchip for alternate output options (LVPECL, LVDS, LVCMOS).
Output Waveform and Connection Diagram define the parameters.
Period Jitter includes crosstalk from adjacent output.
Jitter limits established by Gen 1.1, Gen 2.1, Gen 3.0, and Gen 4.0 PCIe standards.
TEMPERATURE SPECIFICATIONS
Parameters
Temperature Ranges
Operating Temperature Range
Junction Operating Temperature
Storage Temperature Range
Lead Temperature
T
A
T
J
T
S
—
–40
–40
—
–55
—
—
—
—
—
+260
+85
+105
+150
+150
—
°C
°C
°C
°C
°C
Ordering Option I
Ordering Option L
—
—
Soldering, 40s
Sym.
Min.
Typ.
Max.
Units
Conditions
DS20006175A-page 4
2019 Microchip Technology Inc.
DSA557-03/04/05
2.0
PIN DESCRIPTIONS AND CONNECTION DIAGRAMS
DSA557-03 QFN-14 PIN FUNCTION TABLE
Pin Name
OE
NC
NC
VSS
NC
NC
NC
CLK1+
CLK1–
CLK0–
CLK0+
VDD1
VDD0
NC
Pin Type
I
N/A
N/A
P
N/A
N/A
N/A
O
O
O
O
P
P
N/A
Output enable, active-high.
Ground recommended or leave as a NC.
Ground recommended or leave as a NC.
Ground.
Ground recommended or leave as a NC.
Ground recommended or leave as a NC.
Ground recommended or leave as a NC.
True output of differential pair.
Complement output of differential pair.
Complement output of differential pair.
True output of differential pair.
Power supply for core and output 1 (CLK1+/CLK1–)
Power supply for output 0 (CLK0+/CLK0–)
Ground recommended or leave as a NC.
Description
The descriptions of the pins are listed in
Table 2-1, Table 2-2,
and
Table 2-3.
TABLE 2-1:
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0.1μF
+
VDD
-
14
1
+
Enable
-
2
3
4
5
13
12
11
10
9
8
5
5
CLK0+
CLK0-
6
7
Ropt
CLK1-
CLK1+
Ropt 22Ω
–
33Ω optional
5
5
FIGURE 2-1:
14-Lead QFN Connection Diagram with Two HCSL Outputs.
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