CY28446
Clock Generator for Intel
®
Calistoga Chipset
Features
• Compliant to Intel
®
CK410M
• Selectable CPU frequencies
• Low power differential CPU clock pairs
• 100 MHz Low power differential SRC clocks
• 96 MHz Low power differential DOT clock
• 48 MHz USB clock
• SRC clocks stoppable through OE#
Table 1. Output Configuration Table
CPU
x2/x3
SRC
x9/10
PCI
x5
REF
x1
DOT96
x1
48M
x1
• 33 MHz PCI clocks
• Buffered 14.318 MHz reference clock
• Low-voltage frequency select input
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V Power supply
• 64 pin QFN package
Pin Configuration
FS_B/TEST_MODE
VTTPWRGD#/PD
FS_C/TEST_SEL
PCIF0/ITP_EN
USB_48/FS_A
DOTC_96
DOTT_96
VDD_PCI
VSS_PCI
VSS_PCI
VDD_48
OE1#
PCI0
PCI1
PCI2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VSS_48
SRCT0
SRCC0
OE0#
SRCT1
SRCC1
OEA#
SRCT2
SRCC2
VDD_SRC
VSS_SRC
OE3#
SRCT3
SRCC3
OE6#
PCI_STOP#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDD_SRC
SRCC5
SRCC6
SRCT5
SRCT6
SRCT8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD_SRC
VSS_SRC
SRCC10
CPUC2_ITP/SRCC7
SRCT10
CPUT2_ITP/SRCT7
VDD_PCI
REF
VSS_REF
XIN
XOUT
VDD_REF
SDATA
SCLK
CPU_STOP#
CPUT0
CPUC0
VSS_CPU
VDD_CPU
CPUT1
CPUC1
VSS_SRC
CY28446
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SRCC8
OEB#
SRCC9
SRCT9
....................... Document #: 001-00168 Rev *F Page 1 of 19
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
PCI3
www.silabs.com
CY28446
Table 2. Frequency Table
FS_C
MID
0
0
0
0
MID
MID
MID
1
1
1
FS_B
0
0
1
1
0
0
1
1
0
1
1
FS_A
1
1
1
0
0
0
0
1
x
0
1
Reserved
Hi-Z
REF/2
REF/2
100
Hi-Z
REF/8
REF/8
33
Hi-Z
REF/24
REF/24
14.318
Hi-Z
REF
REF
100
Hi-Z
REF/8
REF/8
96
Hi-Z
REF
REF
48
CPU
100
133
166
200
SRC/SATA
100
100
100
100
PCIF/PCI
33
33
33
33
REF
14.318
14.318
14.318
14.318
LCD
100
100
100
100
DOT96
96
96
96
96
USB
48
48
48
48
Hi-Z
REF
REF
.......................Document #: 001-00168 Rev *F Page 2 of 19
CY28446
Pin Description
Pin No.
1
Name
VSS_48
Type
GND
Ground for outputs.
O, DIF
100 MHz Differential serial reference clocks
Description
2, 3, 5, 6, 8, SRC(0:3, 5:6, 8:10)
9, 13, 14, 18, [T/C]
19, 20, 21,
22, 23, 25,
26, 27, 28
4, 7, 12, 15,
24, 64
10, 17, 29,
11, 30, 33
16
31, 32
OE[0, 1, 3, 6, A, B]#
VDD_SRC
VSS_SRC
PCI_STP#
I, PU
3.3V LVTTL input for enabling assigned SRC clock (active LOW)
PWR
3.3V power supply for outputs.
GND
Ground for outputs.
I, PU
3.3V LVTTL input for PCI_STP#
Stops SRC and PCI clocks not set to free running in the SMBUS registers.
CPU2_ITPT/SRCT7, O, DIF
Selectable differential CPU clock/100 MHz Differential serial reference clock.
CPU2_ITPC/SRCC7
Selectable via Pin 53 PCIF0/ITP_EN
O, DIF
Differential CPU clock outputs.
PWR
3.3V power supply for outputs.
GND
Ground for outputs.
I, PU
3.3V LVTTL input for CPU_STP# active LOW.
I
I/O,
OD
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
VDD_CPU
VSS_CPU
CPU_STP#
SCLK
SDATA
VDD_REF
XOUT
XIN
VSS_REF
REF
VDD_PCI
PCIF0/ITP_EN
34, 35, 38, 39 CPUT/C[0:1]
36
37
40
41
42
43
44
45
46
47
48, 54
53
PWR
3.3V power supply for outputs.
O, SE
14.318 MHz crystal output.
I
14.318 MHz crystal input.
GND
Ground for outputs.
O,SE
Fixed 14.318 MHz clock output.
PWR
3.3V power supply for outputs.
O, SE
33 MHz clock output
I/O, PD
33 MHz clock output (not stoppable by PCI_STOP#)/3.3V LVTTL input for
selecting pins 31/32 (CPU2_ITP[T/C]/SRC7[T/C])
(sampled on the
VTT_PWRGD# assertion).
0 (default): SRC7[T/C]
1: CPU2_ITP[T/C]
GND
Ground for outputs.
I, PD
3.3V LVTTL input.
This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C, and all I/O configuration pins,. After VTT_PWRGD# (active LOW) assertion,
this pin becomes a real-time input for asserting power-down (active HIGH).
I, PD
3.3V-tolerant input for CPU frequency selection/Selects test mode if pulled to
V
IMFS_C
when VTT_PWRGD# is asserted LOW.
Refer to DC Electrical Specifications table for
V
ILFS_C
,V
IMFS_C
,V
IHFS_C
specifica-
tions.
I/O, PU
Fixed 48 MHz clock output/3.3V-tolerant input for CPU frequency selection.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
PWR
3.3V power supply for outputs.
O, DIF
Fixed 96 MHz clock output.
I, PU
3.3V-tolerant input for CPU frequency selection Selects Ref/N or Tri-state
when in test mode
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
49, 50, 51, 52 PCI[0:3]
55, 59
56
VSS_PCI
VTT_PWRGD#/PD
57
FS_C/TEST_SEL
58
60
61,62
63
USB_48/FS_A
VDD_48
DOT_96[T/C]
FS_B/TEST_MODE
.......................Document #: 001-00168 Rev *F Page 3 of 19
CY28446
Frequency Select Pins (FS_A, FS_B, and FS_C)
Apply the appropriate logic levels to FSA, FSB, and FSC
before CK-PWRGD assertion to achieve host clock frequency
selection. When the clock chip sampled HIGH on CK-PWRGD
and indicates that VTT voltage is stable then FSA, FSB, and
FSC input values are sampled. This process employs a
one-shot functionality and once the CK-PWRGD sampled a
valid HIGH, all other FSA, FSB, FSC and CK-PWRGD transi-
tions are ignored except in test mode
optional. Clock device register changes are made at system
initialization if required. The interface cannot be used during
system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest byte (most significant bit first) with
the ability to stop after complete byte has been transferred. For
byte write and byte read operations, the system controller
accesses individually indexed bytes. The offset of the indexed
byte is encoded in the command code, as described in
Table 3.
The block write and block read protocol is outlined in
Table 4
while
Table 5
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up, making this interface
Table 3. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation.
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'.
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
46
....
....
....
....
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Byte Count–8 bits
(Skip this step if I
2
C_EN bit set)
Acknowledge from slave
Data byte 1–8 bits
Acknowledge from slave
Data byte 2–8 bits
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N–8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
....
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeat start
Slave address–7 bits
Read = 1
Acknowledge from slave
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
Stop
Block Read Protocol
Description
.......................Document #: 001-00168 Rev *F Page 4 of 19
CY28446
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
Slave address–7 bits
Read
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Control Registers
Byte 0: Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
Description
CPU2_ITP[T/C]/SRC7[T/C] CPU2_ITP[T/C]/SRC[T/C]7 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]6
SRC[T/C]6 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]5
SRC[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
Reserved
Reserved
SRC[T/C]3
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]2
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]1
SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]0
SRC[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enable
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
@Pup
1
1
1
1
1
1
1
Name
PCIF0
DOT_96[T/C]
USB_48
REF
Reserved
CPU[T/C]1
CPU[T/C]0
PCIF0 Output Enable
0 = Disable, 1 = Enable
DOT_96 MHz Output Enable
0 = Disable (Tri-state), 1 = Enable
USB_48 Output Enable
0 = Disable, 1 = Enable
REF Output Enable
0 = Disable, 1 = Enable
Reserved
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enable
Description
.......................Document #: 001-00168 Rev *F Page 5 of 19
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